Method for producing trenches for DRAM cell configurations

A method for producing trenches for manufacturing storage capacitors in DRAM cell configurations, which comprises:

• forming a first mask layer having a thickness between 100 nm and 250 nm from a layer selected from the group consisting of a polysilicon layer and a crystalline silicon layer;
• forming a second mask layer having a thickness greater than 850 nm from an SiO2 layer;
• providing the second mask layer underlying the first mask layer;
• placing the first mask layer and the underlying second mask layer on a wafer that forms a semiconductor substrate;
• providing a resist mask having a hole pattern and placing the resist mask on the first mask layer;
• performing a first etching process to selectively etch the first mask layer with respect to the resist mask and to structure recesses in the first mask layer in correspondence with the hole pattern of the resist mask;
• and
• subsequently, performing a second etching process to selectively etch the second mask layer with respect to the first mask layer and to structure recesses in the second mask layer through the recesses of the first mask layer.