Copper reflow process
AssigneeIntel Corporation
InventorDonald S. Gardner
Life of this patent
Estimating the term…
Abstract
A manufacturable method for forming a highly reliable electrical interconnection. An electrical interconnection pattern is first formed in a dielectric layer on a semiconductor substrate as recessed regions in the dielectric layer. A conductive layer primarily comprising copper is thereafter deposited over the surface and in the recessed regions of the dielectric layer. The conductive layer is then reflowed to fill the recessed regions of the dielectric layer with substantially no void formation. This reflow process may also be used to improve the step coverage of any such copper layer deposited over the surface of a substrate to be used in conjunction with alternate techniques for forming electrical interconnections including photoresist patterning and etch.
Claims21
A method of forming an electrical conductor over a semiconductor substrate, said method comprising the steps of:
- (a) forming a recessed region in a first layer above said semiconductor substrate;
- (b) forming a second layer above said first layer such that at least a portion of said second layer is formed in said recessed region, said second layer comprising copper as its primary element;
- and
- (c) reflowing said second layer by exposing said second layer to a temperature in the range of approximately 200° C.-800° C.
The method of claim l further comprising the step of forming a barrier layer between at least a portion of said first layer and at least a portion of said second layer.
A method of forming an electrical conductor over a semiconductor substrate, said method comprising the steps of:
- (a) forming a recessed region in a first layer over said semiconductor substrate, said first layer comprising a dielectric material;
- (b) sputtering a second layer above said first layer such that at least a portion of said second layer is deposited in said recessed region, said second layer comprising copper as its primary element;
- (c) reflowing said second layer by exposing said second layer to a temperature in the range of approximately 200° C.-800° C.;
- and
- (d) etching at least a portion of said second layer which exists outside said recessed region such that said second layer becomes isolated within said recessed region.
A method of forming an electrical conductor over a semiconductor substrate, said method comprising the steps of:
- (a) forming a first layer over said semiconductor substrate, said first layer comprising copper as its primary element;
- (b) reflowing said first layer;
- (c) patterning said first layer;
- and
- (d) etching said first layer.
Dependencies are inferred from the claim text.