Semiconductor wafer, method for processing the same and method for manufacturing semiconductor device
AssigneeSeiko Epson Corporation
InventorKatsumi Mori
Life of this patent
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Abstract
A method is provided for processing a semiconductor wafer having a chip region where chips are formed and a non-chip region where chips are not normally formed. The method includes the steps of forming trench isolation regions in the semiconductor wafer, and forming dummy trench isolation regions in at least a part of the non-chip region of the semiconductor wafer.
Claims13
A method for processing a semiconductor wafer defining a chip region and a non-chip region, the method comprising the steps of:
- forming trench isolation regions in the semiconductor wafer;
- and
- forming dummy trench isolation regions in at least a part of the non-chip region of the semiconductor wafer.
A method for processing a semiconductor wafer defining a chip region and a non-chip region, the method comprising the steps of:
- (A) forming trench isolation regions in the semiconductor wafer, wherein the step (A) comprises the steps of:
- (a) forming a polishing stopper layer having a specified pattern over the semiconductor wafer;
- (b) forming trenches in the chip region and dummy trenches in at least a portion of the non-chip region in the semiconductor wafer using at least the polishing stopper layer as a mask;
- (c) forming a dielectric layer over the semiconductor wafer and filling the trenches and the dummy trenches with the dielectric layer;
- and
- (d) polishing the dielectric layer using the polishing stopper layer as a stopper.
A method for processing a semiconductor wafer defining a chip region and a non-chip region, the method comprising the steps of:
- (A) forming trench isolation regions in the semiconductor wafer, wherein the step (A) comprises the steps of:
- (h) forming a polishing stopper layer over the semiconductor wafer;
- (i) forming a resist layer over the polishing stopper layer;
- (j) exposing the resist layer in the chip region and at least one specified portion of the non-chip region;
- (k) developing the resist layer;
- (l) removing the polishing stopper layer in a specified pattern using the resist layer as a mask;
- (m) etching the semiconductor wafer using at least the polishing stopper layer to form trenches in the chip region and dummy trenches in the non-chip region;
- (n) forming a dielectric layer over the semiconductor wafer and filling the trenches and the dummy trenches with the dielectric layer;
- and
- (o) polishing the dielectric layer using the polishing stopper layer as a stopper.
A semiconductor wafer comprising:
- a chip region and a non-chip region, wherein at least one portion of the non-chip region includes a dummy trench isolation region.
A method for manufacturing a semiconductor device, the method comprising the steps of:
- defining a chip region and a non-chip region in a semiconductor wafer;
- and
- forming trench isolation regions in the chip region and in at least a part of the non-chip region of the semiconductor wafer.
A method for manufacturing a semiconductor device, the method comprising the steps of:
- defining a chip region and a non-chip region in a semiconductor wafer;
- and
- forming trench isolation regions in the chip region and in at least a part of the non-chip region of the semiconductor wafer, wherein the step of forming the trench isolation regions comprises the steps of:
- (h) forming a polishing stopper layer over the semiconductor wafer;
- (i) forming a resist layer over the polishing stopper layer;
- (j) exposing the resist layer in the chip region and at least one specified portion of the non-chip region;
- (k) developing the resist layer;
- (l) removing the polishing stopper layer in a specified pattern using the resist layer as a mask;
- (m) etching the semiconductor wafer using at least the polishing stopper layer to form trenches in the chip region and dummy trenches in the non-chip region;
- (n) forming a dielectric layer over the semiconductor wafer and filling the trenches and the dummy trenches with the dielectric layer;
- and
- (o) polishing the dielectric layer using the polishing stopper layer as a stopper.
A method for processing a semiconductor wafer, the method comprising the steps of:
- defining a chip region and a non-chip region in the semiconductor wafer;
- and
- forming trench isolation regions in the chip region and in at least a part of the non-chip region of the semiconductor wafer.
A method for processing a semiconductor wafer, the method comprising the steps of:
- defining a chip region and a non-chip region in the semiconductor wafer;
- and
- forming trench isolation regions in the chip region and in at least a part of the non-chip region of the semiconductor wafer, wherein the step of forming the trench isolation regions comprises the steps of:
- (a) forming a polishing stopper layer over the semiconductor wafer;
- (b) forming a resist layer over the polishing stopper layer;
- (c) exposing the resist layer in the chip region and at least one specified portion of the non-chip region;
- (d) developing the resist layer;
- (e) removing the polishing stopper layer in a specified pattern using the resist layer as a mask;
- (f) etching the semiconductor wafer using at least the polishing stopper layer to form trenches in the chip region and the non-chip region;
- (g) forming a dielectric layer over the semiconductor wafer and filling the trenches with the dielectric layer;
- and
- (h) polishing the dielectric layer using the polishing stopper layer as a stopper.
Dependencies are inferred from the claim text.