Passive multiplexor test structure for integrated circuit manufacturing
AssigneePDF Solutions, Inc.
InventorsBrian E. Stine, Christopher Hess, Larg H. Weiland
Life of this patent
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Abstract
A test structure for analyzing failures due to fabrication induced defects in integrated circuits includes a matrix of bit cells formed by word lines and bit lines. An associated word line probe pad is electrically connected to each word line and an associated bit line probe pad electrically connected to each bit line. A test structure is electrically connected between a word line and a bit line of an associated bit cell. Each test structure has at least one variable attribute which is used to detect defects and create yield models.
Claims23
A method for analyzing failures due to fabrication induced defects in integrated circuits comprising the steps of:
- a) providing a matrix of first lines and second lines, each first line having an associated first line probe pad electrically connected thereto, and each second line having an associated second line probe pad electrically connected thereto;
- and
- b) providing a plurality of passive test structures, each associated with a respective first line and a respective second line, each test structure electrically connected between a first line and a second line, and each test structure having at least one variable attribute which is used to detect defects and create yield models.
A method for analyzing failures due to fabrication induced defects in integrated circuits comprising:
- a) providing a source of electrical current, said current source having a first electrical potential of a first magnitude and a second electrical potential of a second magnitude which differs from the first magnitude by a predetermined amount;
- b) providing a matrix of first lines and second lines, each first line having an associated first line probe pad electrically connected thereto, and each second line having an associated second line probe pad electrically connected thereto, all first line probe pads being electrically connected to the first potential of said current source and each second line probe pad being selectively, individually electrically connectable to the second potential of said current source;
- c) providing test structures associated with said first and second lines, each test structure electrically connected between a respective first line and a respective second line, and each test structure having at least one variable attribute which is used to detect defects and create yield models;
- and
- d) electrically connecting a current measuring device to each first line for measuring the current through the test structure associated with said first line.
A method for analyzing failures due to fabrication induced defects in integrated circuits comprising the steps of:
- a) providing a matrix of first lines and second lines, each first line having an associated first line probe pad electrically connected thereto, and each second line having an associated second line probe pad electrically connected thereto;
- and
- b) providing a plurality of test structures, each associated with a respective first line and a respective second line, each test structure electrically connected between a first line and a second line, and each test structure having at least one variable attribute which is used to detect defects and create yield models, wherein two or more of the plurality of test structures have respectively different attribute values for the at least one variable attribute, wherein step (b) includes varying the value of at least one of the following:
- 1) metal box 1 border x and y directions;
- 2) spacing of metal 2 neighbor to via chain;
- 3) misalignment of via to metal 1, x and y directions;
- 4) misalignment of via to metal 2, x and y directions;
- 5) spacing of metal 1 neighbor to via chain;
- 6) spacing of via to nearest via;
- 7) metal 2 border x and y directions;
- 8) via hole size;
- 9) metal 2 runner length;
- 10) metal 1 neighbor line width perpendicular to via chain;
- 11) metal 2 neighbor line width parallel to via chain;
- 12) metal 2 neighbor line width perpendicular to via chain;
- 13) metal 2 runner length;
- and
- 14) metal 1 neighbor line width perpendicular to via chain.
Dependencies are inferred from the claim text.