P-type LDMOS device with buried layer to solve punch-through problems and process for its manufacture
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChih-Feng Huang, Kuo-Su Huang
Life of this patent
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Abstract
P-type LDMOS devices have been difficult to integrate with N-type LDMOS devices without adding an extra mask because the former have been unable to achieve the same breakdown voltage as the latter due to early punch-through. This problem has been overcome by preceding the epitaxial deposition of N− silicon onto the P− substrate with an additional process step in which a buried N+ layer is formed at the surface of the substrate by ion implantation. This N+ buried layer significantly reduces the width of the depletion layer that extends outwards from the P− well when voltage is applied to the drain thus substantially raising the punch-through voltage.
Claims11
A process for manufacturing an LDMOS device, comprising the sequential steps of:
- providing a P− substrate having a surface;
- forming a N+ buried layer that extends downwards from said surface to a depth;
- forming an epitaxial layer of N− silicon that extends upwards from said substrate surface;
- forming a P− base region in the epitaxial layer;
- outside said base region, forming a P+ source and a polysilicon gate located between said source and said base region;
- and
- in the base region, forming a P+ drain.
A process for manufacturing an LDMOS device, comprising the sequential steps of:
- providing a P− substrate having a surface;
- forming a N+ buried layer that extends downwards from said surface;
- forming an epitaxial layer of N− silicon, having an upper surface, that extends upwards from said substrate surface;
- forming a P+ base region that extends downwards from said upper surface into the epitaxial layer;
- forming a P+ junction isolation boundary that extends from said upper surface to the P-substrate;
- forming first and second outer areas of field oxide, each touching an isolation boundary, and an inner area of field oxide wholly within the P− base region such that the first outer area is separated from said inner area by a first gap, the second outer area is separated from said inner area by a second gap, and the first gap is wider than the second gap;
- on said upper surface, in the first gap, forming a layer of gate oxide;
- on said layer of gate oxide, depositing a layer of polysilicon;
- patterning said polysilicon, and all gate oxide not protected therewith, to form a gate pedestal;
- by ion implantation through a mask, forming a N+ region that is contiguous with the first outer area and that extends downwards from said upper surface;
- by ion implantation through a mask, forming a P+source region, that is contiguous with said N+ region, and a P+ drain region located in the second gap, both P+ regions extending downwards from said upper surface;
- and
- forming metallic source, gate, and drain contacts.
Dependencies are inferred from the claim text.