Method for production of a memory cell arrangement
AssigneeSiemens Aktiengesellschaft
InventorsFranz Hofmann, Wolfgang Krautschneider, Josef Willer
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Abstract
A method for production of a memory cell arrangement which includes vertical MOS transistors as memory cells, wherein the information is stored utilizing at least three different threshold voltage values of the transistors by multi-level programming. One threshold voltage value is realised by the thickness of the gate dielectric in the sense of a thick oxide transistor and the other threshold voltage values are realised by different channel dopings. The arrangement can be produced with as area requirement for each memory cell of 2 F2 (F: minimum structure size).
Claims7
A method for production of a memory cell arrangement, comprising the steps of:
- forming strip-like trenches which essentially run in parallel in a main area of a substrate which includes at least in a region of the main area semiconductor material which is doped by a first conductivity type,
- forming MOS transistors which are vertical with respect to the main area of the substrate, the MOS transistors being formed on the sides of the trenches, said MOS transistors functioning as memory cells and have respective first, second and third threshold voltage values depending upon stored information of the respective MOS transistors, and
- a first memory cell of said memory cells possessing said first threshold voltage value depending upon a thickness of a gate dielectric which differs from a gate dielectric thickness of said MOS transistors not having said first threshold value, a second memory cell of said memory cells having said second threshold voltage value depending upon a second gate dielectric thickness and a channel doping, a third memory cell of said memory cells having said third threshold voltage value depending upon a different channel doping than said channel doping of said second memory cell.
Dependencies are inferred from the claim text.