Method for manufacturing a ferroelectric random access memory device

A method for manufacturing a ferroelectric random access memory (FeRAM) device, the method comprising, in order, the steps of:

• a) preparing a substrate on which a first insulating layer is formed;
• b) forming a buffer layer on the first insulating layer;
• c) forming a bottom electrode layer on the buffer layer;
• d) forming a ferroelectric dielectric layer on the bottom electrode layer;
• e) forming a top electrode layer on the ferroelectric dielectric layer;
• f) forming a top electrode photoresist pattern;
• g) etching the top electrode layer using the top electrode photoresist pattern as an etch mask to form a top electrode and to expose a surface of the ferroelectric dielectric layer adjacent the top electrode;
• h) removing the top electrode photoresist pattern;
• i) forming a capacitor photoresist pattern, the capacitor photoresist pattern covering both the top electrode and a portion of the exposed surface of the ferroelectric dielectric layer adjacent the top electrode;
• j) etching the ferroelectric dielectric layer, the bottom electrode layer and the buffer layer using the capacitor photoresist pattern as an etch mask to form a capacitor structure comprising a top electrode, a ferroelectric dielectric, a bottom electrode, and a buffer, and to expose a surface of the first insulating layer adjacent the capacitor structure;
• k) removing the capacitor photoresist pattern;
• l) forming a second insulating layer, the second insulating layer covering the top electrode, the exposed surface of the ferroelectric dielectric and the exposed surface of the first insulating layer;
• m) forming a contact photoresist pattern on the second insulating layer, the contact photoresist pattern comprising a storage node contact opening and a cell plate contact opening, the storage node opening being positioned above a portion of the top electrode and the cell plate contact opening being positioned above a portion of the ferroelectric dielectric adjacent the top electrode;
• n) etching the second insulating layer using a first set of etch parameters to expose a portion of the top electrode below the storage node contact opening and to expose a portion of the ferroelectric dielectric below the cell plate contact opening;
• o) etching the exposed portion of the ferroelectric dielectric using a second set of etch parameters, the second set of etch parameters being unequal to the first set of etch parameters to expose a portion of the bottom electrode below the cell plate contact opening;
• p) removing the contact photoresist pattern;
• q) depositing a conductive layer on the second insulating layer, the exposed portion of the top electrode and the exposed portion of the bottom electrode;
• r) forming an interconnection photoresist pattern on the conductive layer;
• s) etching the conductive layer using the interconnection photoresist pattern as an etch mask to form an interconnection pattern;
• and
• t) removing the interconnection photoresist pattern.