Stacked semiconductor integrated circuit device and manufacturing method thereof

#The present invention relates generally to semiconductor integrated circuits having a decreased electrode-to-electrode distance and a manufacturing method thereof More particularly, but not exclusively, the invention relates to metal oxide semiconductor (MOS) transistors having the structure of narrowed gate electrode distance with the capability of eliminating the flow of leak current in a difffusion layer region between adjacent gate electrodes while increasing the operating speed of semiconductor integrated circuits.

#Recent advances of micropatterning/microfabrication technology in the manufacture of semiconductor elements have enabled attainment of higher integration of an increased number of devices on one chip, while simultaneously supporting the fundamental technical basis for development of high-performance devices.

#One approach to meet the needs is to further increase the integration density of currently available stacked metal oxide semiconductor (MOS) transistors. The term “stacked MOS transistors” as used herein may refer to those transistors with the device structure having a plurality of gate electrodes extending in parallel in the direction of the gate length. By way of example, since MOS transistors are such that the “nature” of transistors (gate current) is determinable depending upon the ratio of gate width to gate length, it is possible to generate a required gate current which increases in magnitude as the gate width increases. Forming a plurality of gate electrodes of a constant gate width in a diffusion layer region of limited dimension may enable formation of plural MOS transistors. More specifically, forming two parallel gate electrodes having the same gate width on a substrate surface corresponding to such difflusion layer region makes it possible to configure circuitry including a combination of two MOS transistors.

#A more complete appreciation of the present invention and many of its attendant advantages will be readily obtained by reference to the following detailed description considered in connection with the accompanying drawings, which.

#FIG. 1 is a diagram showing a plan view of one typical prior art semiconductor IC device.

#FIG. 2 shows an enlarged plan view of part of the IC device shown in FIG. 1.

#Some embodiments of the present invention will be described with reference to FIGS. 8-19 in the figures of the accompanying drawing.

#FIG. 8 shows a plan view of a semiconductor integrated circuit (C) device in accordance with one preferred embodiment of the invention, FIG. 9 is a pictorial representation of part of the FIG. 8 device. Also, FIGS. 10-18 illustrate typical device structures obtainable at major steps in the manufacture of the IC devices for explanation of fabrication methodology also embodying the invention.

#Referring first to FIG. 8, a NAND IC chip is configured from p-type metal oxide semiconductor (pMOS) and n-type MOS (nMOS) transistors on a semiconductor substrate 1 made typically of silicon as can be seen from the planar surface thereof. The silicon substrate 1 has in its top surface a p-type diffusion layer 24 and n-type diffusion layer 23 with gate electrode lines 7 and 9 being formed to overlie diffusion layers 23 and 24. These layers have thereon several electrode contact portions 27, selected ones of which are electrically connected together by a corresponding one of metal lead patterns 35. Due to the inherent IC configuration, the distance between adjacent gate electrodes of nMOS transistors with a reference character “A” adhered thereto is narrowed in a way such that it is less than the distance “B” between the gate electrodes of pMOS transistors. The former gate-to-gate distance “A” may typically be 200 nm.