Bipolar-CMOS (BiCMOS) process for fabricating integrated circuits

A process for fabricating an integrated circuit, comprising:

• forming N-type and P-type buried layers in a silicon substrate;
• forming an epitaxial layer above the N-type and P-type buried layers;
• forming a plurality of wells in the epitaxial layer;
• forming a first polysilicon layer over the epitaxial layer;
• forming at least two MOS transistors in at least two of the wells in the epitaxial layer;
• forming a first bipolar transistor in another well of the epitaxial layer, wherein forming the first bipolar transistor includes outdiffusing impurities from the first polysilicon layer to form an emitter of the first bipolar transistor;
• forming a second polysilicon layer;
• forming a second bipolar transistor in yet another well of the epitaxial layer, wherein forming the second bipolar transistor includes outdiffusing impurities from the second polysilicon layer to form an emitter of the second bipolar transistor;
• and
• forming a third bipolar transistor in still another well of the epitaxial layer.

A process for fabricating an integrated circuit, comprising:

• forming N-type and P-type buried layers in a silicon substrate;
• forming an epitaxial layer above the N-type and P-type buried layers;
• forming a plurality of wells in the epitaxial layer;
• forming at least two MOS transistors in the wells in the epitaxial layer, wherein gates of the MOS transistors are formed of a first level of polysilicon;
• forming a high-gain bipolar transistor in another well of the epitaxial layer, wherein an emitter of the high-gain bipolar transistor is formed by outdiffusing impurities from the first layer of polysilicon;
• forming a low-gain bipolar transistor in yet another well of the epitaxial layer, wherein an emitter of the low-gain bipolar transistor is formed by outdiffusing impurities from the second layer of polysilicon;
• and
• forming an intermediate-gain bipolar transistor in still another well of the epitaxial layer, wherein an emitter of the intermediate-gain bipolar transistor is formed by ion implantation into the epitaxial layer.

A process for fabricating an integrated circuit, comprising:

• forming N-type and P-type buried layers in a silicon substrate;
• forming an epitaxial layer above the N-type and P-type buried layers;
• forming a plurality of wells in the epitaxial layer;
• forming a first layer of polysilicon;
• forming at least two MOS transistors in the wells in the epitaxial layer, wherein forming the at least two MOS transistors includes forming gates of the at least two MOS transistors from the first level of polysilicon and forming implanting ions to form the source and drain regions of at least one of the MOS transistors;
• forming a first bipolar transistor in another well of the epitaxial layer, wherein forming the first bipolar transistor includes outdiffusing impurities from the first layer of polysilicon to form an emitter;
• forming a second layer of polysilicon;
• forming a second bipolar transistor in yet another well of the epitaxial layer, wherein forming a second bipolar transistor includes outdiffusing impurities from the second layer of polysilicon to form an emitter;
• and
• forming a third bipolar transistor in still another well of the epitaxial layer, wherein forming the third bipolar transistor includes simultaneously forming an emitter of the third bipolar transistor with the source and drain regions of the at least one MOS transistor.

A process for fabricating an integrated circuit, comprising:

• forming N-type and P-type buried layers in a silicon substrate, wherein forming the N-type buried layers include performing at least one of ion implantation or diffusion;
• forming an epitaxial layer above the N-type and P-type buried layers;
• forming a plurality of wells in the epitaxial layer;
• forming a first layer of polysilicon;
• forming at least two MOS transistors in the wells in the epitaxial layer, wherein forming the at least two MOS transistors includes forming gates of the at least two MOS transistors from the first level of polysilicon and forming implanting ions to form the source and drain regions of at least one of the MOS transistors;
• forming a first bipolar transistor in another well of the epitaxial layer, wherein forming the first bipolar transistor includes outdiffusing impurities from the first layer of polysilicon to form an emitter;
• forming a second layer of polysilicon;
• forming a second bipolar transistor in yet another well of the epitaxial layer, wherein forming a second bipolar transistor includes outdiffusing impurities from the second layer of polysilicon to form an emitter;
• and
• forming a third bipolar transistor in still another well of the epitaxial layer, wherein forming the third bipolar transistor includes simultaneously forming an emitter of the third bipolar transistor with the source and drain regions of the at least one MOS transistor.

A process for fabricating an integrated circuit, comprising:

• forming N-type and P-type buried layers in a silicon substrate;
• forming an epitaxial layer above the N-type and P-type buried layers;
• forming a plurality of wells in the epitaxial layer;
• forming a MOS transistor in one of the wells in the epitaxial layer, wherein forming the MOS transistor includes forming a source and a drain;
• forming a first bipolar transistor in a first of the wells of the epitaxial layer;
• forming a second bipolar transistor in a second of the wells of the epitaxial layer;
• forming a third bipolar transistor in a third of the wells of the epitaxial layer, wherein forming the third bipolar transistor includes forming an emitter;
• and
• wherein forming the source and drain of the MOS transistor and forming the emitter of the third bipolar transistor are simultaneously formed by ion implantation into the epitaxial layer.