US 6,475,846 B1Granted

Method of making floating-gate memory-cell array with digital logic transistors

AssigneeTexas Instruments Incorporated

InventorsGiulio Marotta, Giovanni Santin, Michael C. Smayling, Misako A. Matsuoka, Satoru Fukawa

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Abstract

A nonvolatile memory array is encased in a P-well, and the P-well encased in a deep N-well, the two wells separating the memory array from the integrated circuit substrate and from the other circuitry of the integrated circuit. At the same time the deep N-well is formed for the nonvolatile memory array, deep N-wells are formed for the high-voltage P-channel transistors of the logic circuitry. At the same time the P-well is formed for the nonvolatile memory array, P-wells are formed for the low-voltage N-channel transistors. The memory array contains nonvolatile cells of the type used in ultra-violet-erasable EPROMs. During erasure, the isolated-well formation allows the source, the drain and the channel of selected cells to be driven to a positive voltage. The isolated well is also driven to a positive voltage equal to, or slightly greater than, the positive voltage applied to the source and drain, thus eliminating the field-plate breakdown-voltage problem.

Claims10

Dependent claims

A method for making a nonvolatile, floating-gate memory with logic transistors in a face of a semiconductor body, comprising the steps of:

forming first and second opposite-conductivity-type diffusion regions having a first depth in said semiconductor body, said first and second opposite-conductivity-type diffusion regions doped to have primarily a second conductivity-type opposite said first conductivity-type;
forming first and second same-conductivity-type diffusion regions having a second depth in said semiconductor body, said first same-conductivity-type diffusion region encased in said first opposite-conductivity-type diffusion region, said second same-conductivity-type region separate from said first and second opposite-conductivity-type diffusion regions, said first and second same-conductivity-type diffusion regions doped to have primarily said first conductivity-type;
forming at least one floating-gate memory cell in and on said first same-conductivity-type diffusion region;
forming at least one high-voltage logic transistor in said second opposite-conductivity-type diffusion region;
and
forming at least one low-voltage logic transistor in said second same-conductivity-type diffusion region.

3 more elements

Dependencies are inferred from the claim text.