Method of fabricating integrated circuits, providing improved so-called saw bows
AssigneeKoninklijke Philips Electronics N.V.
InventorsEwald Bergler, Josef Preishuber-Pfluegl, Reinhard Fetzer, Haiko Klepzig
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AssigneeKoninklijke Philips Electronics N.V.
InventorsEwald Bergler, Josef Preishuber-Pfluegl, Reinhard Fetzer, Haiko Klepzig
Estimating the term…
An integrated circuit (6) has a semiconductor die (47) and an integrated circuit configuration (16) realized on the semiconductor die (47) and situated within bounding faces (52, 53, 54, 55) of the semiconductor die (47), in which two conductor track sections (34, 35) have been provided, which issue from the integrated circuit configuration (16) and which each extend up to a bounding face (55) and which are required for the application of a useful signal (BR1) utilized for test purposes during the fabrication of the integrated circuit (6), and in which an additional conductor track section (41) has been provided, which is disposed adjacent the two conductor track sections (34, 35) and which issues from the integrated circuit configuration (16) and extends toward a bounding surface (55) and preferably up to this bounding face (55) and which serves for the application of a spurious signal (BR2) which interferes with testing.
A method of fabricating integrated circuits (2, 3, 4, 5, 6, 7, 8, 9, 10), in which a reticular pattern (11) of separation strips (12, 13, 14, 15) on the semiconductor wafer (1) is defined, and in which a plurality of juxtaposed integrated circuit configurations (16) are formed between the separation strips (12, 13, 14, 15) on the semiconductor wafer (1), and in which during the fabrication of the integrated circuits (2, 3, 4, 5, 6, 7, 8, 9, 10) at least one conductor track (33, 37;
Dependencies are inferred from the claim text.