Defect analysis method and process control method

A defect analysis method of a device which includes an integrated circuit formed on each of a plurality of chips on a wafer through a plurality of processes, said defect analysis method comprising the steps of:

• (a) after each of at least one process out of said plurality of processes, detecting a new defect due to said at least one process and occurring in a new area of said wafer other than an area of a defect occurring at a previous process and its vicinity;
• (b) after said plurality of processes are completed, making one of defective and non-defective judgement on said integrated circuit of each of said plurality of chips;
• (c) judging one of a presence and absence of said new defect satisfying a predetermined identifying condition in each of said plurality of chips, for each of said at least one process;
• (d) classifying said plurality of chips into four groups including non-defective chip with no said new defect, defective chip with no said new defect, non-defective chip with said new defect and defective chip with said new defect on a basis of a combination of the judgment of said step (b) and the judgment of said step (c), for each of said at least one process;
• (e) calculating a number of new defective chips considered to be caused only by said new defect of said at least one process, on a basis of the classification of said step (d);
• (f) calculating a critical rate of said new defect of said at least one process at which a chip is considered to become defective, on a basis of the classification of said step (d);
• and
• (g) calculating a number of process defective chips considered to be caused by said at least one process, on a basis of the classification of said step (d) and said critical rate,
• wherein said step (c) is performed a plurality of times for each of a plurality of detection sizes as a referred detection size,
• wherein said predetermined identifying condition includes a condition that a defect be of said referred detection size or more;
• and
• said steps (d) to (g) are performed said plurality of times corresponding to said step (c) which was performed said plurality of times, so that data for analysis including the number of said new defective chips, said critical rate, and the number of said process defective chips is obtained for each of said plurality of detection sizes for each of said at least one process, wherein
• said at least one process includes a predetermined number, which is at least two, of processes which are identical in content but different in inspection apparatus to be used for inspection at said step (a);
• said data for analysis is obtained for each of said predetermined number of processes;
• and
• said critical rate includes said predetermined number of critical rates of a same detection level corresponding to said predetermined number of processes,
• said defect analysis method further comprising the step of:
• (h) recognizing a difference in sensitivity between said predetermined number of inspection apparatuses by comparing said predetermined number of critical rates of the same detection level.

A storage medium for storing a defect analysis program and for having a defect analysis system with a computer execute a defect analysis processing of a device which includes an integrated circuit formed on each of a plurality of chips on a wafer through a plurality of processes,

• said defect analysis system comprising:
• at least one inspection apparatus for detecting a position of coordinates of a defect on said wafer, for determining a size of said defect after each of said plurality of processes, and for outputting defect information;
• a tester for making a defective/non-defective judgement on each of said integrated circuit on said plurality of chips on said wafer after all of said plurality of processes are completed, and for outputting defective/non-defective judgment information;
• and
• a control portion for executing said defect analysis program upon receipt of said defect information and said defective/non-defective judgment information,
• said storage medium for storing said defect analysis program and for having said computer execute the steps of:
• (a) after each of at least one process out of said plurality of processes, detecting a new defect due to said at least one process and occurring in a new area of said wafer other than an area of a defect occurring at a previous process and its vicinity, on a basis of said defect information;
• (b) after said plurality of processes are completed, making a defective/non-defective judgement on said integrated circuit on each of said plurality of chips, on a basis of said defective/non-defective judgment information;
• (c) judging one of a presence and absence of said new defect satisfying a predetermined identifying condition in each of said plurality of chips, for each of said at least one process;
• (d) classifying said plurality of chips into four groups including non-defective chip with no said new defect, defective chip with no said new defect, non-defective chip with said new defect and defective chip with said new defect on a basis of a combination of the judgment of said step (b) and the judgment of said step (c), for each of said at least one process;
• and
• (e) calculating a number of new defective chips considered to be caused only by said new defect of said at least one process, on a basis of the classification of said step (d).

A storage medium for storing a defect analysis program which has a defect analysis system with a computer for executing a defect analysis processing of a device,

• said device including an integrated circuit formed on each of a plurality of chips on a wafer through a plurality of processes,
• said defect analysis system comprising:
• at least one inspection apparatus for detecting a position of coordinates of a defect on said wafer and a size of said defect after each of said plurality of processes, and for outputting defect information;
• a tester for making a defective/non-defective judgement on said integrated circuit on each of said plurality of chips on said wafer after said plurality of processes are completed, and for outputting defective/non-defective judgment information;
• and
• a control portion for executing said defect analysis program upon receipt of said defect information and said defective/non-defective judgment information,
• wherein at least one of said control portion and said at least one inspection apparatus has a function to detect a new defect due to said at least one process, occurring in a new area of said wafer other than an area of a defect occurring at a previous process and its vicinity, after each of at least one process out of said plurality of processes on a basis of said defect information,
• said storage medium for storing said defect analysis program and for having said computer execute the steps of:
• (a) receiving a new defect due to said at least one process;
• (b) after said plurality of processes are completed, making a defective/non-defective judgement on said integrated circuit on each of said plurality of chips, on a basis of said defective/non-defective judgment information;
• (c) judging one of a presence and absence of said new defect satisfying a predetermined identifying condition in each of said plurality of chips, for each of said at least one process;
• (d) classifying said plurality of chips into four groups including non-defective chip with no said new defect, defective chip with no said new defect, non-defective chip with said new defect, and defective chip with said new defect on a basis of a combination of the judgment of said step (b) and the judgment of said step (c), for each of said at least one process;
• and
• (e) calculating a number of new defective chips considered to be caused only by said new defect of said at least one process, on a basis of the classification of said step (d).