Magnetic memory device

A magnetic memory device comprising:

• a magnetic memory cell array comprised of a plurality of divided memory cell arrays each having a plurality of magnetic memory cells,
• first and second data lines,
• a plurality of word lines crossing said first and/or second data lines, and
• a plurality of bit lines crossing said first and/or second data lines,
• wherein each of said magnetic memory cells is fabricated by first and second tunnel junction sections and a cell selection semiconductor element, each of said first and second tunnel junction sections being formed of a stack of a pinned layer having a magnetization direction fixed and a recording layer in which a magnetic direction changes depending on an external magnetic field, said stack has single or multiple tunnel junctions, said first tunnel junction section has a first end and a second end opposite to each other in the stacking direction, said second tunnel junction section has a third end and a fourth end opposite to each other in the stacking direction, said first end of said first tunnel junction section is connected to said first data line, said third end of said second tunnel junction section is connected to said second data line, said second end of said first tunnel junction section and said fourth end of said second tunnel junction section are connected to said bit line via said cell selection semiconductor element.

A magnetic memory device comprising:

• a magnetic memory cell array comprised of a plurality of divided memory cell arrays, each having a plurality of magnetic memory cells,
• first and second data lines,
• a plurality of word lines crossing said first and/or second data lines,
• a plurality of bit lines arranged in parallel with said first and/or second data lines,
• wherein each of said magnetic memory cells is fabricated by first and second tunnel junction sections and a cell selection semiconductor element, each of said first and second tunnel junction portions is formed of a stack of a pinned layer having a magnetization direction fixed and a record layer in which a magnetic direction changes depending on an external magnetic field, said stack has single or multiple tunnel junctions, said first tunnel junction section has a first end and a second end opposite to each other in the stacking direction, said second tunnel junction portion has a third end and a fourth end opposite to each other in the stacking direction, said first end of said first tunnel junction section is connected to said first data line, said third end of said second tunnel junction section is connected to said second data line, said second end of said first tunnel junction portion and said fourth end of said second tunnel junction portion are connected to said bit line via said cell selection semiconductor element.

A magnetic memory device comprising:

• a magnetic memory cell array comprised of a plurality of divided memory cell arrays, each of said divided memory cell arrays being fabricated by a plurality of magnetic memory cells, first and second subsidiary data lines disposed in parallel to each other, a plurality of word lines crossing said first and/or second data lines, and a plurality of subsidiary bit lines parallel to said first and second data lines,
• wherein each of said magnetic memory cells is formed of first and second tunnel junction section and a cell selection semiconductor element, each of said first and second tunnel junction section comprises a stack of a pinned layer having a magnetization layer pinned therein and a record layer in which a magnetization direction changes depending on an external magnetization field, said first tunnel junction section has a first end and a second end opposite to each other in the stacking direction, said second tunnel junction section has a third end and a fourth end opposite to each other in the stacking direction, said first end of said first tunnel junction section is connected to said first subsidiary data line, said third end of said second tunnel junction section is connected to said second subsidiary data line, said second end of said first tunnel junction portion and said fourth end of said second tunnel junction section are connected to a corresponding one of said subsidiary bit lines, said magnetic memory device has a plurality of selection transistors for selectively connecting said first and second subsidiary data lines, said subsidiary bit lines, first and second data lines, and a bit line.

A magnetic memory device comprising:

• a magnetic memory cell array comprised of a plurality of divided memory cell arrays each having a plurality of magnetic memory cells,
• first and second data lines crossing to each other;
• a plurality of word lines and a plurality of bit lines crossing to each other;
• wherein each of said magnetic memory cells is fabricated by first and second tunnel junction sections and a cell selection semiconductor element, each of said first and second tunnel junction sections being formed of a stack of a pinned layer having a magnetization direction pinned therein and a record layer in which a magnetic direction changes depending on an external magnetic field, said stack has single or multiple tunnel junctions, said first tunnel junction portion has a first end and a second end opposite to each other in the stacking direction, said second tunnel junction portion has a third end and a fourth end opposite to each other in the stacking direction, said first end of said first tunnel junction section is connected to said first data line, said third end of said second tunnel junction section is connected to said second data line, said second end of said first tunnel junction section and said fourth end of said second tunnel junction section are connected to said bit line via said cell selection semiconductor element.

A magnetic memory device comprising:

• a tunnel junction section including:
• a stack of a first pinned layer having a magnetization direction fixed, a first tunnel barrier adjacent to said first pinned layer, a first magnetic layer which is opposite to said first pinned layer via said first tunnel barrier and in which a magnetization direction changes depending on an external magnetic field, a second magnetic layer which is anti-ferromagnetically coupled to said first ferromagnetic layer and in which a magnetization direction changes depending on the external magnetic field, and a non-magnetic conductive layer interposed between said first and second magnetic layers, for anti-ferromagnetically coupling between said first and second magnetic layers,
• a second tunnel barrier adjacent to said second magnetic layer and
• a second pinned layer opposite to said second magnetic layer via said second tunnel barrier and
• a detection section configured to detect a current difference between a first tunnel current flowing across said first magnetic layer and said first pinned layer and a second tunnel current flowing across said second magnetic layer and said second pinned layer or a load voltage difference in a differential scheme.

A magnetic memory device comprising:

• a tunnel junction including:
• a stack of a first pinned layer having a magnetization direction fixed, a first tunnel barrier adjacent to said first pinned layer, a first magnetic layer which is opposite to said first pinned layer via said first tunnel barrier and in which a magnetization direction changes depending on an external magnetic field, a second magnetic layer which is anti-ferromagnetically coupled to said first ferromagnetic layer and in which a magnetization direction changes depending on the external magnetic field, and a non-magnetic conductive layer interposed between said first and second magnetic layers,
• a second tunnel barrier adjacent to said second magnetic layer and
• a second pinned layer opposite to said second magnetic layer via said second tunnel barrier,
• a bit line electrically connected to all or either of said first magnetic layer, said non-magnetic conductive layer, and said second magnetic layer;
• a first data line electrically connected to said first pinned layer;
• and
• a second data line electrically connected to said second pinned layer.