Static random access memory (SRAM)

An SRAM cell comprising:

• a semiconductor body;
• a plurality of electrically interconnected pairs of CMOS transistors, each one of a pair of the transistors having:
• (a) a gate channel region disposed between a source region and a drain region, wherein such regions being horizontally separated by a common region extending vertically beneath a surface of the body;
• (b) a plurality dielectric layers, each one thereof being disposed on opposing surface portions of each one of the pair of gate channel regions;
• (c) a plurality of gate electrode conductive regions, a first one thereof being disposed on a corresponding one of the plurality of dielectric layers;
• and
• wherein one of the plurality of gate conductor regions is disposed in the common region and provides a common gate conductor region for the pair of transistors.

An SRAM cell, comprising:

• a plurality of electrically interconnected pairs of MOS transistors disposed in a semiconductor body, each pair of transistors having:
• a gate channel region disposed between a source region and a drain region, such regions being horizontally separated by a common region extending vertically beneath a surface of the body;
• a plurality dielectric layers, each one thereof being disposed on opposing surface portions of each one of the pair of gate channel regions;
• a plurality of gate electrode conductive regions, a first one thereof being disposed on a corresponding one of the plurality of dielectric layers;
• an insulating layer extending horizontally beneath the surface of the semiconductor body such insulating layer being disposed beneath the pair of transistors.

A semiconductor structure comprising:

• a semiconductor body;
• a pair of CMOS transistors, such pair of transistors having a common gate region extending vertically into the semiconductor body;
• wherein each one of the transistors comprises:
• a gate channel region extending vertically into the semiconductor body between a source region and a drain region, such regions being adjacent the common gate region;
• and
• a second gate region;
• wherein the gate channel region of a first one of the pair of transistor is disposed between the common gate region and the second gate region of the first one of the pair of transistors;
• and
• wherein the gate channel region of a second one of the pair of transistor is disposed between the common gate region and the second gate region of the second one of the pair of transistors.