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AssigneeLSI Logic Corporation
InventorsYauh-Ching Liu, Helmut Puchner, Ruggero Castagnetti, Weiran Kong, Lee Phan, Franklin Duan, Steven Michael Peterson
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An integrated circuit structures such as an SRAM construction wherein the soft error rate is reduced comprises an integrated circuit structure formed in a semiconductor substrate, wherein at least one N channel transistor is built in a P well adjacent to one or more deep N wells connected to the high voltage supply and the deep N wells extend from the surface of the substrate down into the substrate to a depth at least equal to that depth at which alpha particle-generated electron-hole pairs can effectively cause a soft error in the SRAM cell. For a 0.25 μm SRAM design having one or more N wells of a conventional depth not exceeding about 0.5 μm, the depth at which alpha particle-generated electron-hole pairs can effectively cause a soft error in the SRAM cell is from 1 to 3 μm. The deep N well of the 0.25 μm SRAM design, therefore, extends down from the substrate surface a distance of at least about 1 μm, and preferably at least about 2 μm. In a preferred embodiment, the implantation of the substrate to form the deep N well of the improved SRAM of the invention is carried out in a manner which will cause straggle, i.e., cause the doped volume comprising the deep N well to broaden at its base. Such a broadened base deep N well will have enhanced opportunity to collect electrons generated by the alpha particle collision with the substrate. This deep N well with a broadened base can be formed either by increasing the implant energy or by tilting the substrate with respect to the axis of the implant beam while implanting the substrate to form the deep N well.
An improved SRAM construction in a P-type semiconductor substrate, wherein at least one N channel transistor is built in a P well between at least two deep N wells and said deep N wells extend from a surface of the substrate down into the substrate to a depth at least twice the horizontal spacing between said deep N wells, whereby said depth of said deep N wells is at least equal to that depth at which electrons from alpha particle-generated electron-hole pairs can effectively cause a soft error in the SRAM construction, so that said deep N wells inhibit occurrence of said soft errors.
An improved SRAM construction in a P-type semiconductor substrate, wherein at least one N channel transistor is built in a P well positioned between and adjacent to two deep N wells, wherein said deep N wells each extend from the surface of the substrate down into said P-type substrate beyond the depth of said P well to a depth, from the surface of said substrate, at least equal to twice the horizontal spacing between said deep N wells, and said deep N wells extend laterally toward one another at their respective bases an amount insufficient to impede the formation of a depletion region between said deep N wells and that portion of said P-type substrate between said deep N wells below said P well when a potential is applied between said deep N wells and said P-type substrate, to thereby enhance collection of electrons from alpha particle-generated electron-hole pairs to thereby inhibit occurrence of soft errors in said SRAM cell.
An improved SRAM construction in a P-type semiconductor substrate, wherein at least one N channel transistor is built in a P well between at least two deep N wells and said deep N wells extend from a surface of the substrate down into the substrate to a depth at least twice the horizontal spacing between said deep N wells, whereby said depth of said deep N wells is at least equal to that depth at which electrons from alpha particle-generated electron-hole pairs can effectively cause a soft error in the SRAM construction, so that said deep N wells inhibit occurrence of said soft errors, and said respective depths of said at least two deep N wells are sufficient to cause each of said N wells to extend laterally at its base to enhance the opportunity of said deep N wells to collect electrons generated by said alpha particle-generated electron-hole pairs.
An improved SRAM construction in a P-type semiconductor substrate, wherein at least one N channel transistor is built in a P well adjacent to at least one deep N well formed on two opposite sides of said P well, wherein said deep N wells extend from the surface of the substrate down into the substrate beyond the depth of said shallow P well to a depth of at least 1 μm and wherein said deep N wells each has a depth from the surface of said substrate at least equal to the horizontal spacing between said deep N wells in said substrate, and further wherein the depth of said deep N wells is sufficient to cause each of said N wells to extend laterally at its base to enhance the pick up, by said deep N wells, of electrons generated by said alpha particle-generated electron-hole pairs, to thereby collect electrons from alpha particle-generated electron-hole pairs to thereby inhibit occurrence of soft errors in said SRAM cell.
An improved SRAM construction in a P-type semiconductor substrate, wherein at least one N channel transistor is built in a P well adjacent to at least one deep N well formed on two opposite sides of said P well, wherein said deep N well extends from the surface of the substrate down into the substrate beyond the depth of said shallow P well to a depth of at least 1 μm to thereby collect electrons from alpha particle-generated electron-hole pairs to thereby inhibit occurrence of soft errors in said SRAM cell, and further wherein said deep N wells are each formed with a portion of each deep N well extending, in the region of the substrate beneath said P well, toward the other of said deep N wells, said portion of each deep N well extending toward said other deep N well having a shape formed by tilting the substrate during the implantation of said deep N wells.
Dependencies are inferred from the claim text.