Semiconductor device in which memory cells and peripheral circuits are provided on the same circuit

A semiconductor device in which memory cells and transistors are provided on the same substrate, and comprising:

• a semiconductor substrate of a first conductivity type;
• a memory cell section complementary transistor provided on said semiconductor substrate;
• and
• a core section complementary transistor provided on said semiconductor substrate, said core section complementary transistor having:
• a first well of a second conductivity type provided in said semiconductor substrate;
• a first core section MOS transistor provided on said first well of the second conductivity type, said first core section MOS transistor having source-drain regions of the first conductivity type;
• a second core section MOS transistor provided on said semiconductor substrate, said second core section MOS transistor having source-drain regions of the second conductivity type;
• a device separation film which separates said first core section MOS transistor and said second core section MOS transistor from each other;
• and
• a well of the first conductivity type provided under a part of said device separation film which is closer to said second core section MOS transistor, said well of the first conductivity type having an impurity concentration higher than that of said semiconductor substrate;
• wherein said memory cell section complementary transistor comprises:
• a second well of the first conductivity type and a second well of the second conductivity type provided in said semiconductor substrate;
• a first memory cell section MOS transistor provided on said second well of the second conductivity type, said first memory cell section MOS transistor having source-drain regions of the first conductivity type;
• and
• a second memory cell section MOS transistor provided on said second well of the first conductivity type, said second memory cell section MOS transistor having source-drain regions of the second conductivity type, and an impurity concentration of said first well of the first conductivity type and that of said second well of the first conductivity type are substantially equal to each other;
• and
• further comprising a third well of the second conductivity type provided under a part of said device separation film which is closer to said first core section MOS transistor, an impurity concentration of said third well of the second conductivity type being higher than that of said first well of the second conductivity type.