Memory cell configuration and corresponding production process

A memory cell configuration, comprising:

• a semiconductor substrate having a main face and defined longitudinal and transverse directions;
• a multiplicity of memory cells formed in said semiconductor substrate;
• a plurality of mutually parallel bit-line trenches extending in the longitudinal direction in said main face of said semiconductor substrate, said bit-line trenches having bottoms each formed with a first conductive region, peaks each formed with a second conductive region of a same conductivity type as the first conductive region is provided, and walls with a respective intermediately located channel region;
• and
• word lines extending in the transverse direction along said main face of said semiconductor substrate, through specific said bit-line trenches, for activating transistors formed in said specific bit-line trenches;
• and
• additional dopant introduced in said trench walls of said bit-line trenches located between said word lines, for increasing a corresponding transistor turn-on voltage to suppress leakage currents.