US 6,472,693 B1Granted

Semiconductor device and method of manufacturing the same

AssigneeMitsubishi Denki Kabushiki Kaisha

InventorsHideki Takahashi, Yoshifumi Tomomatsu

Life of this patent

Estimating the term…

Loading patent…

Abstract

The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly, an object of the present invention is to reduce an ON voltage while ensuring a wide operating area and sustaining a high breakdown voltage. To achieve this object, a semiconductor base body is divided into a first MOS region and a second MOS region. In the first MOS region, a p base layer, an n+ emitter layer and a p+ layer are provided in an upper main surface of the semiconductor base body. In the second MOS region, a p base layer, an n layer and a p+ layer are provided. When a positive gate voltage is applied to a gate electrode in order to turn on the device, since the p base layer and the emitter electrode are cut off, a main current does not flow in the p base layer. Therefore, a hole accumulation effect is enhanced and the ON voltage is reduced. When a negative gate voltage is applied in order to turn off the device, since a channel region is inverted, the main current constituted of residual carriers flows in both p base layers. Therefore, a wide operating area is ensured. Since no n layer surrounding the p base layer exists, unlike in a CSTBT, there is no problem of degradation in breakdown voltage.

Claims28

Dependent claims

A semiconductor device, comprising:

a semiconductor base body defining an upper main surface and a lower main surface,
wherein said semiconductor base body comprises
a first semiconductor layer of a first conductivity type exposed to said lower main surface;
a second semiconductor layer of a second conductivity type formed on said first semiconductor layer and exposed to said upper main surface;
a third semiconductor layer of the first conductivity type selectively formed in said upper main surface, being shallower than said second semiconductor layer;
a fourth semiconductor layer of the second conductivity type selectively formed in a surface to which said third semiconductor layer is exposed, being shallower than said third semiconductor layer and inside said third semiconductor layer;
a fifth semiconductor layer of the first conductivity type selectively formed in said upper main surface, being shallower than said second semiconductor layer and away from said third semiconductor layer;
a sixth semiconductor layer of the second conductivity type selectively formed in a surface to which said fifth semiconductor layer is exposed, being shallower than said fifth semiconductor layer and inside said fifth semiconductor layer;
and
a seventh semiconductor layer of the first conductivity type selectively formed in a surface to which said sixth semiconductor layer is exposed, being shallower than said sixth semiconductor layer and inside said sixth semiconductor layer,
wherein a surface to which said third semiconductor layer is exposed in said upper surface includes a first region and a second region separated by said fourth semiconductor layer, and at least said second region of them is sandwiched by a surface to which said fourth semiconductor layer is exposed and a surface to which said second semiconductor layer is exposed,
said device further comprising:
a first gate electrode opposed to said second region with a first insulating film sandwiched therebetween;
a second gate electrode opposed to a surface to which said sixth semiconductor layer is exposed in said upper surface with a second insulating film sandwiched therebetween;
a first main electrode connected to said first region, said fourth semiconductor layer and said seventh semiconductor layer;
and
a second main electrode connected to sa id lower main surface, and
wherein a transistor including said second semiconductor layer, said fifth semiconductor layer and said sixth semiconductor layer does not operate even when a predetermined voltage is applied to said second gate electrode and said first main electrode, respectively.

15 more elements

A semiconductor device, comprising:

a semiconductor base body defining an upper main surface and a lower main surface,
wherein said semiconductor base body comprises
a first semiconductor layer of a first conductivity type exposed to said lower main surface;
a second semiconductor layer of a second conductivity type formed on said first semiconductor layer and exposed to said upper main surface;
a third semiconductor layer of the first conductivity type selectively formed in said upper main surface, being shallower than said second semiconductor layer;
a fourth semiconductor layer of the second conductivity type selectively formed in a surface to which said third semiconductor layer is exposed, being shallower than said third semiconductor layer and inside said third semiconductor layer;
a fifth semiconductor layer of the first conductivity type selectively formed in said upper main surface, being shallower than said second semiconductor layer and away from said third semiconductor layer;
a sixth semiconductor layer of the second conductivity type selectively formed in a surface to which said fifth semiconductor layer is exposed, being shallower than said fifth semiconductor layer and inside said fifth semiconductor layer;
and
a seventh semiconductor layer of the first conductivity type selectively formed in a surface to which said sixth semiconductor layer is exposed, being shallower than said sixth semiconductor layer and inside said sixth semiconductor layer,
wherein a surface to which said third semiconductor layer is exposed in said upper surface includes a first region and a second region separated by said fourth semiconductor layer, and at least said second region of them is sandwiched by a surface to which said fourth semiconductor layer is exposed and a surface to which said second semiconductor layer is exposed,
said device further comprising:
a first gate electrode opposed to said second region with a first insulating film sandwiched therebetween;
a second gate electrode opposed to a surface to which said sixth semiconductor layer is exposed in said upper surface with a second insulating film sandwiched therebetween;
a first main electrode connected to said first region, said fourth semiconductor layer and said seventh semiconductor layer;
and
a second main electrode connected to said lower main surface, and
wherein said sixth semiconductor layer and said first main electrode are not in contact with each other.

15 more elements

Dependencies are inferred from the claim text.