Method and system for etching tunnel oxide to reduce undercutting during memory array fabrication

A method for etching gate oxide when forming a select gate region and a word-line region during transistor fabrication, comprising the steps of:

• (a) depositing a gate oxide on a substrate;
• (b) depositing a tunnel oxide mask over a portion of the gate oxide;
• and
• (c) performing a combination dry/wet-etch to remove the gate oxide uncovered by the tunnel oxide mask over the word-line region, the combination dry/wet-etch including the steps of,
• (i) performing dry-etch at less than approximately 200 electron volts to remove approximately two thirds of the gate oxide, and
• (ii) performing a wet-etch for a time sufficient to remove any remaining gate oxide, thereby minimizing tunnel oxide undercut and allowing the select gate region to be placed closer to the word-line region.