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US 6,472,283 B1Granted
MOS transistor processing utilizing UV-nitride removable spacer and HF etch
AssigneeAdvanced Micro Devices, Inc.
InventorsEmi Ishida, Srinath Krishman, Ming Yin Hao, Effiong Ibok
Life of this patent
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Abstract
Submicron-dimensioned MOS and/or CMOS transistors are fabricated by a process employing removable sidewall spacers made of a material, such as UV-nitride, which is readily etched in its as-deposited, undensified state but difficult-to-etch in its thermally annealed, densified state. The as-deposited, undensified spacers are removed by etching with dilute aqueous HF after implantation of moderately or heavily-doped source/drain regions but prior to annealing of the implants for dopant diffusion/activation and lattice damage relaxation. Lightly- or moderately doped, shallow-depth source/drain extensions are implanted and annealed after spacer removal.
Claims19
A method of manufacturing a semiconductor device, which method comprises the sequential steps of:
- (a) providing a device precursor structure comprising a semiconductor substrate of a first conductivity type and a layer stack formed on a portion of a surface of said substrate, said layer stack comprising:
- i. a thin gate insulating layer in contact with said substrate surface;
- and
- ii. a gate electrode layer formed on said gate insulating layer, said layer stack comprising a pair of opposing side surfaces and a top surface;
- (b) forming a first pair of insulative, tapered sidewall spacers on each of said pair of opposing side surfaces, said first pair of sidewall spacers comprising a first dielectric material in an as-deposited, undensified state, the first pair of sidewall spacers having lower ends on the surfaces of the substrate;
- (c) thermally treating said first pair of sidewall spacers to convert said first dielectric material from its as-deposited, undensified state to an annealed, densified state;
- (d) forming a second pair of insulative, tapered sidewall spacers on each of said first pair of sidewall spacers, said second sidewall spacers comprising a second dielectric material in an as-deposited, undensified state, the second pair of sidewall spacers having lower ends on the surface of the substrate;
- (e) selectively introducing dopant impurities of a second, opposite conductivity type into exposed portions of said substrate surface adjacent said first and second pairs of sidewall spacers to form a pair of spaced-apart heavily-doped implants in said substrate;
- (f) selectively removing the as-deposited, undensified second pair of sidewall spacers by an etching process;
- (g) thermally treating said pair of spaced-apart, heavily-doped implants to form a pair of heavily-doped source/drain junction regions in said substrate at a predetermined depth below said substrate surface, each of said heavily-doped source/drain junction regions being laterally spaced from a respective proximal edge of said gate insulting layer by a distance substantially equal to the combined width of said lower ends of said first and second pairs of sidewall spacers;
- (h) introducing second, opposite conductivity type dopant impurities into exposed portions of said substrate surface intermediate said gate insulating layer and said heavily-doped source/drain junction regions to form lightly-or moderately doped source/drain extension implants, and
- (i) thermally treating said lightly- or moderately-doped source/drain extension implants to form a pair of shallow-depth, lightly- or moderately-doped source/drain extensions in said substrate, each of said shallow-depth, lightly-doped extensions extending from a proximal edge of a respective source/drain junction region to beneath a respective proximal edge of said gate insulating layer.
9 more elements
A method of manufacturing a silicon-based MOS-type transistor, which method comprises the sequential steps of:
- (a) providing a MOS transistor precursor structure comprising a silicon semiconductor wafer substrate of a first conductivity type and a layer stack formed on a portion of a surface of said wafer, said layer stack comprising:
- i. a thin gate insulating layer comprising a silicon oxide layer about 25-50 Å thick in contact with said wafer surface;
- and
- (b) a gate electrode layer comprising heavily-doped polysilicon formed on said gate insulating layer, said layer stack comprising a pair of opposing side surfaces and a top surface;
- (c) forming a first pair of insulative, tapered sidewall spacers on each of said pair of opposing side surfaces, said first pair of sidewall spacers comprising a first dielectric material selected from silicon oxides, silicon nitrides, and silicon oxynitrides, said first dielectric material having an as-deposited, undensified state;
- (d) thermally treating said pair of sidewall spacers to convert said first dielectric material from its as-deposited, undensified state to an annealed, densified state;
- (e) forming a second pair of insulative, tapered sidewall spacers on each of said first pair of sidewall spacers, said second sidewall spacers comprising a UV-nitride material having an as-deposited, undensified state but difficult-to-etch in its thermally treated, densified state;
- (f) selectively implanting dopant impurities of a second, opposite conductivity type into exposed portions of said wafer surface adjacent said first and second pairs of sidewall spacers to form a pair of spaced-apart, heavily-doped implants in said wafer;
- (g) selectivity removing the as-deposited, undensified UV-nitride second pair of sidewall spacers by etching with dilute aqueous HF;
- (h) performing rapid thermal annealing to diffuse and activate the dopant impurities implanted in step (c), thereby forming a pair of heavily-doped, relatively deep, source/drain junction regions in said wafer, each of said heavily doped source/drain junction regions being laterally spaced from a respective proximal edge of said gate insulating layer by a distance substantially equal to the combined width of the lower ends of said first and second pairs of sidewall spacers adjacent said wafer surface;
- (i) implanting second, opposite conductivity type dopant impurities into exposed portions of said wafer surface intermediate said gate insulating layer and said heavily-doped source/drain regions to form lightly- or moderately-doped source/drain extension implants therein;
- and
- (j) performing thermal annealing to diffuse and activate the dopant impurities implanted in step on), thereby forming a pair of shallow-depth, lightly- or moderately-doped source/drain extension regions in said wafer, each of said shallow-depth, lightly-or moderately-doped source/drain extensions extending from a proximal edge of a respective source/drain region to beneath a respective proximal edge of said gate insulating layer.
10 more elements
Dependencies are inferred from the claim text.