DRAM cell having storage capacitor contact self-aligned to bit lines and word lines

A method for forming a dynamic random access memory (DRAM) cell having a storage capacitor contact self-aligned to bit lines and word lines comprising:

• providing a semiconductor substrate, the substrate having formed thereon isolation regions and active regions;
• forming an access transistor on an active region of the substrate, the access transistor having a first terminal, a second terminal, and a gate, the gate being fabricated from a first polysilicon layer, the gate containing at least one word line;
• forming initial source and drain regions in the substrate by a first implantation;
• depositing a first sidewall dielectric layer over the word line;
• forming first insulating sidewall spacer structures on the side surfaces of the word line;
• completing the formation of the source and drain regions by a second implantation;
• forming an etch barrier layer over the substrate including the word line and the source and drain regions;
• depositing a first interlayer dielectric layer over the etch barrier layer;
• planarizing the first interlayer dielectric layer;
• forming a buried contact hole through the first interlayer dielectric layer to the drain region;
• depositing a second polysilicon layer, the second polysilicon layer being deposited so as to extend into the buried contact hole and forming the buried contact;
• forming a second insulating layer over the second polysilicon layer;
• forming at least one bit line, the bit line being fabricated from the second polysilicon layer;
• depositing a second insulating sidewall dielectric layer over the bit line;
• forming second insulating sidewall spacer structures on the side surfaces of the bit line;
• depositing a second interlayer dielectric layer over the bit line;
• planarizing the second interlayer dielectric layer;
• forming a self-aligned capacitor contact hole, said capacitor contact hole being self-aligned to the word line and the bit line and the source region;
• depositing a third polysilicon layer, the third polysilicon layer covering the second interlayer dielectric layer and extending into the capacitor contact hole and contacting the source region;
• forming capacitor storage elements, the capacitor storage elements being formed from the third polysilicon layer;
• forming a capacitor dielectric layer over the capacitor storage elements;
• depositing a fourth polysilicon layer over the capacitor dielectric layer;
• and
• forming a capacitor top plate, the capacitor top plate being formed from the fourth polysilicon layer.