Method for fabricating a bipolar transistor of the self-aligned double-polysilicon type with a heterojunction base and corresponding transistor

A method for fabricating a self-aligned double-polysilicon type bipolar transistor with a heterojunction base comprising the steps of:

• forming a semiconductor substrate with an active region;
• forming an isolating region that surrounds the active region of the semiconductor substrate;
• and
• forming a semiconducting heterojunction region on top of the active region and the isolating region by non-selective epitaxy, wherein the heterojunction region comprises a layer made of a silicon-germanium alloy surmounted by a silicon layer and a layer made of a silicon-germanium alloy surmounted by a silicon layer;
• forming a stack on top of the active region comprising the sub-steps of:
• disposing an etch stop layer on top of the active region, wherein the stop layer includes disposing a stop layer formed from the same material as a material forming the at least one upper insulating layer of the stack;
• and
• disposing a protective layer on top of the at least one upper insulating layer and on top of the outer periphery of the emitter window, wherein the protective layer is made of a material which is different than a material forming the etch stop layer and wherein in the step of replacing the etch stop layer by an electrically conducting replacement material at the outer periphery of the emitter window includes replacing the the protective layer with the electrically conducting replacement material;
• disposing a polysilicon layer having the same type of conductivity as the semiconducting heterojunction region, wherein the polysilicon layer is overdoped with respect to the semiconducting heterojunction region;
• disposing at least one upper insulating layer;
• defining an emitter window with an outer periphery above the active region by etching the stack so as to stop at the etch stop layer;
• replacing the etch stop layer by an electrically conducting replacement material at the outer periphery of the emitter window;
• and
• forming an emitter region resting partially on the at least one upper insulating layer.

A method for fabricating a self-aligned double-polysilicon type bipolar transistor with a heterojunction base comprising the steps of:

• forming a semiconductor substrate with an active region;
• forming an isolating region that surrounds the active region of the semiconductor substrate;
• and
• forming a semiconducting heterojunction region on top of the active region and the isolating region by non-selective epitaxy, wherein the heterojunction region;
• forming a stack on top of the active region comprising the sub-steps of:
• disposing an etch stop layer on top of the active region;
• disposing a polysilicon layer having the same type of conductivity as the semiconducting heterojunction region, wherein the polysilicon layer is overdoped with respect to the semiconducting heterojunction region;
• disposing at least one upper insulating layer;
• defining an emitter window with an outer periphery above the active region by etching the stack so as to stop at the etch stop layer;
• replacing the etch stop layer by an electrically conducting replacement material at the outer periphery of the emitter window and wherein the etch stop layer includes replacing the etch stop layer by isotropical etching so that the stop layer under the polysilicon layer is locally removed over a length (L) which is at least five times greater than a thickness of the replacement material;
• and
• forming an emitter region resting partially on the at least one upper insulating layer.

A method for fabricating a self-aligned double-polysilicon type bipolar transistor with a heterojunction base, the transistor comprising a semiconducting heterojunction region lying over an active region of a semiconductor substrate and over an isolating region delimiting the active region, and incorporating an intrinsic base region, wherein the semiconducting region forms an upper surface, the method comprising the steps of:

• forming an emitter window with an outer periphery above the active region, by etching a stack formed from layers of:
• an etch stop layer on top of the active region;
• a polysilicon layer on top of the etch stop layer having the same type of conductivity as the semiconducting heterojunction region, wherein the polysilicon layer is overdoped with respect to the semiconducting heterojunction region;
• and
• an upper insulating layer on top of the polysilicon layer;
• replacing the etch stop layer by an electrically conducting replacement material at the outer periphery of the emitter window;
• and
• forming an emitter region resting partially on the upper insulating layer.