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US 6,469,328 B2Granted
Semiconductor memory device
AssigneeFujitsu Limited
InventorsTsuyoshi Yanai, Yoshio Kajii, Takashi Ohkawa
Life of this patent
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Abstract
A semiconductor memory device is constructed to include a memory cell formed by a plurality of transistors, wherein each of gate wiring layers of all of the transistors forming the memory cell is arranged to extend in one direction.
Claims14
A semiconductor memory device comprising:
- a memory cell formed by a plurality of transistors, gate wiring layers of all of the transistors forming said memory cell being arranged to extend in one direction, wherein:
- of the transistors forming said memory cell, first transistors which are coupled to word lines are arranged on an outer side of second transistors which are coupled to a power supply, within the memory cell, and
- the gate wiring layers of at least two of said second transistors which are coupled to the power supply are connected to each other,
- a plurality of power lines, a first one of which running within the memory cell, two word lines running on both sides of the first power line,
- a second power line intersecting the first power line,
- and two bit line pairs running on both sides of the second power line;
- and
- wherein a plurality of memory cells are arranged in an array, an adjacent memory cell is arranged adjacent to a certain memory cell, and a source/drain of the transistor, forming said adjacent memory cell and a bulk layer of a substrate contact are used in common by reversing a layout of said certain cell with respect to both an x-axis direction and a y-axis direction.
5 more elements
A semiconductor memory device comprising:
- a memory cell formed by a plurality of transistors,
- gate wiring layers of all of the transistors forming said memory cell being arranged to extend in one direction, wherein:
- of the transistors forming said memory cell, first transistors which are coupled to word lines are arranged on an outer side of second transistors which are coupled to a power supply, within the memory cell,
- the gate wiring layers of at least two of said second transistors which are coupled to the power supply are connected to each other,
- a plurality of power lines, a first one of which running within the memory cell,
- a plurality of signal lines,
- two word lines running on both sides of the first power line,
- a second power line intersecting the first power line,
- two bit line pairs running on both sides of the second power lines;
- a plurality of memory cells being arranged in an array, and
- an adjacent memory cell being arranged adjacent to a certain memory cell,
- said power lines and said signal lines with respect to said adjacent memory cell are used in common with said certain memory cell by reversing a layout of said certain memory cell with respect to both an x-axis direction and a y-axis direction.
9 more elements
Dependencies are inferred from the claim text.