Low resistivity titanium silicide structures
AssigneeMicron Technology, Inc.
InventorYongjun Hu
Life of this patent
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Abstract
Methods and apparatus for forming a conductor layer utilize an implanted matrix to form C54-titanium silicide. Word line stacks formed by the methods of the invention are used in sub-0.2 micron line width applications, interconnects, and silicided source/drain regions, among other applications, and have a lower resistivity and improved thermal stability.
Claims32
A semiconductor structure for providing a low resistivity conductive layer, the semiconductor structure comprising:
- a substrate;
- a gate oxide layer, the gate oxide layer coupled to the substrate;
- a titanium silicide layer, the titanium silicide layer having a C54 TiSi2 lattice structure, the titanium silicide layer including a low resistivity titanium silicide with a reduced grain size, wherein the reduced grain size is less than about 0.25 microns;
- and
- a semiconductor layer, the semiconductor layer being between the gate oxide layer and the titanium silicide layer, wherein the titanium silicide layer is coupled to the semiconductor layer by a single matrix of nucleation sites.
A semiconductor structure for providing a low resistivity conductive layer, the semiconductive structure comprising:
- a source/drain region, the source/drain region supported by a substrate;
- and
- a titanium silicide layer, the titanium silicide layer having a C54 TiSi2 lattice structure, the titanium silicide layer coupled to the source/drain region by a single matrix of nucleation sites, the titanium silicide layer including a low resistivity titanium silicide with a reduced grain size, wherein the reduced grain size is less than about 0.25 microns.
A semiconductor structure for providing a low resistivity conductive layer, the semiconductive structure comprising:
- a substrate;
- a gate oxide layer, the gate oxide layer coupled to the substrate;
- a silicon based material layer, the silicon based material layer coupled to the gate oxide layer;
- and
- a titanium silicide layer, the titanium silicide layer including a low resistivity titanium silicide with a reduced grain size, the titanium silicide layer coupled to the silicon based material layer by a single matrix of nucleation sites,
- wherein the reduced grain size of the low resistivity titanium silicide is less than about 0.25 microns.
A semiconductor structure for providing a low resistivity conductive layer, the semiconductor structure comprising:
- a source/drain region, the source/drain region supported by a substrate;
- and
- a titanium silicide layer, the titanium silicide layer coupled to the source/drain region by a single matrix of nucleation sites, wherein the titanium silicide layer includes a low resistivity titanium silicide with a reduced grain size, wherein the reduced grain size of the low resistivity titanium silicide layer is less than about 0.25 microns.
A semiconductor layer for providing a low resistivity conductive layer, the semiconductive layer comprising a low resistivity titanium silicide with a reduced grain size, the low resistivity titanium silicide having a single matrix of nucleation sites, wherein the reduced grain size of the low resistivity titanium silicide is less than about 0.25 microns.
A semiconductor layer for providing a low resistivity conductive layer, the semiconductive layer comprising titanium silicide, the titanium silicide having a C54 TiSi2 lattice structure, the titanium silicide having a single matrix of nucleation sites,
- wherein the titanium silicide has a grain size of less than about 0.25 microns.
A integrated circuit having sub-0.25 micron features and a low resistivity conductive layer, the integrated circuit comprising titanium silicide, the titanium silicide having a C54 TiSi2 lattice structure, the titanium silicide having a single matrix of nucleation sites,
- wherein the titanium silicide has a grain size of less than about 0.25 microns.
A integrated circuit having sub-0.25 micron features and a low resistivity conductive layer, the integrated circuit comprising a low resistivity titanium silicide with a reduced grain size, the low resistivity titanium silicide having a single matrix of nucleation sites, wherein the reduced grain size of the low resistivity titanium silicide is less than about 0.25 microns.
An ultra-large scale integrated (ULSI) circuit having low resistivity conductive lines, the ULSI circuit comprising:
- a substrate;
- a gate oxide layer, the gate oxide coupled to the substrate;
- a titanium silicide layer, the titanium silicide layer having a C54 TiSi2 lattice structure, the titanium silicide layer including a low resistivity titanium silicide with a reduced grain size, wherein the reduced grain size of the low resistivity titanium silicide is less than about 0.25 microns;
- and
- a semiconductor layer, the semiconductor layer being between the gate oxide layer and the titanium silicide layer, wherein the titanium silicide layer is coupled to the semiconductor layer by a single matrix of nucleation sites.
An ultra-large scale integrated (ULSI) circuit having low resistivity conductive lines, the ULSI circuit comprising:
- a substrate;
- a gate oxide layer, the gate oxide layer coupled to the substrate;
- a silicon based material layer, the silicon based material layer coupled to the gate oxide layer;
- and
- a titanium silicide layer, the titanium silicide layer including a low resistivity titanium silicide with a reduced grain size, the titanium silicide layer coupled to the silicon based material layer by a single matrix of nucleation sites,
- wherein the reduced grain size of the low resistivity titanium silicide is less than about 0.25 microns.
Dependencies are inferred from the claim text.