Byte-switch structure for EEPROM memories

A memory structure including a plurality of EEPROM cells and having a byte-switch structure, the memory structure comprising:

• a control gate line;
• a byte control gate line coupled to control gate electrodes of the memory cells of a given byte;
• a switch MOS transistor having a drain and a drain terminal, a gate and a gate terminal, and a source and a source terminal, the drain terminal coupled to the control gate line, the source terminal coupled to the byte control gate line, and the gate terminal coupled to a respective word line;
• the drain of the switch MOS transistor formed as a first doped region of a first conductivity type formed in a semiconductor layer on a first side of the respective word line, the drain being disposed under the control gate line as perceived from a first direction;
• the source of the switch MOS transistor formed as a second doped region of the first conductivity type formed in the semiconductor layer on a second side of the respective word line, the source being disposed under the control gate line when perceived from the first direction;
• a contact opening disposed between the control gate line and the source, the contact opening structured to electrically couple the source and the byte control gate line and remain insulated from the control gate line;
• and
• an isle including:
• an insulating layer disposed on the semiconductor layer and over the drain of the switch MOS transistor having an opening therein,
• a lower polysilicon layer disposed on the insulating layer and having an opening therein,
• an interpoly dielectric layer disposed over the lower polysilicon layer and having an opening therein, and
• an upper polysilicon layer disposed over the interpoly dielectric layer;
• wherein the control gate line is coupled to the upper polysilicon layer, and wherein the upper polysilicon layer directly contacts the drain of the switch MOS transistor by extending through the openings in the interpoly dielectric layer, the lower polysilicon layer and the insulating layer.

In an EEPROM device having a semiconductor substrate including a plurality of floating gate transistor memory cells made with lower and upper polysilicon layers and having the memory cells of each byte with control gates coupled to one another, a byte-switch transistor comprising:

• a drain coupled to a respective control gate line and disposed within the width of the control gate line;
• a source disposed within the width of the control gate line, coupled to a respective strip of the upper polysilicon layer, and spaced apart from the drain, a portion of the strip disposed underneath the control gate line when perceived from a first direction;
• and
• a contact having an etched lower polysilicon layer, an insulating layer, an interpoly dielectric layer and a part of the strip of upper polysilicon layer such that the part of the polysilicon layer directly contacts the source region of the byte-switch transistor.