SRAM-based semiconductor integrated circuit testing element

A semiconductor integrated circuit device used as a testing element comprising:

• a static random access memory including N channel MOS transistors as transfer gate transistors, and complementary MOS circuits each composed of a P channel MOS transistor and an N channel MOS transistor, first multi-layered wirings connecting the N channel MOS transistors as transfer gate transistors, the P channel MOS transistor and the N channel MOS transistor of the complementary MOS circuits with each other, and opening holes communicating the multi-layered wirings with each other;
• and
• a group of a type of semiconductor integrated circuits each including a P channel MOS transistor and an N channel MOS transistor, second multi-layered wirings connecting the P channel MOS transistor and the N channel MOS transistor of each of said semiconductor integrated circuits with each other, and opening holes communicating the second multi-layered wirings with each other,
• wherein an area of a gate including a source region, a drain region and a channel region of each of the N channel MOS transistors of the transfer gate transistors and the P channel MOS transistor and the N channel MOS transistor of each of the complementary MOS circuits of the random access memory is greater than an average area of gates each including a source region, a drain region and a channel region of each of the P channel MOS transistors and the N channel MOS transistors of the semiconductor integrated circuits,
• wherein a length of each of the wirings of the random access memory is greater than an average length of the wirings of the semiconductor integrated circuits, and
• wherein the number of the opening holes of the random access memory is greater than an average number of the opening holes of the semiconductor integrated circuits.