Self-aligned silicide process for reduction of Si consumption in shallow junction and thin SOI electronic devices

A method of forming an ohmic contact comprising the steps of:

• (a) forming a first layer over a semiconductor wafer including at least exposed silicon-containing areas that are not covered by an insulator, said first layer comprising a M—Si—Ge alloy, wherein M is Co, Ni or a combination of Co and Ni, Si is less than 30 atomic % and Ge is less than 20 atomic %;
• (b) first annealing of said first layer to form a metal rich silicide phase of Co2Si or NixSiy over said exposed silicon-containing area wherein x and y are integers in which x is greater than y and Ge is partly in solution and partly segregates out of said silicide phase, said segregated Ge functioning to substantially reduce silicon diffusion from said silicon-containing areas to said silicide during phase transformations in a subsequent second annealing step;
• (c) etching any unreacted M—Si—Ge alloy present on said semiconductor wafer;
• (d) foaming a blanket layer of Si over said silicide and said semiconductor wafer;
• (c) second annealing of said metal rich silicide phase to convert said metal rich silicide phase into its lowest resistance silicide phase;
• and
• (f) removing any remaining non-reacted Si.