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US 6,444,571 B1Granted
Process for fabricating a semiconductor device with improved step coverage and reliability of a lower aluminum line
AssigneeNEC Corporation
InventorYoshiaki Yamamoto
Life of this patent
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Abstract
A lower aluminum line is exposed to a via-hole formed in an inter-level insulating layer, and an outgassing is carried out before deposition for an upper aluminum line connected through the via-hole to the lower aluminum line, wherein the outgassing is carried out at a substrate temperature equal to or less than the maximum substrate temperature in the formation of the inter-level insulating layer so that a hillock and a whisker due to the thermal stress do not take place in the lower aluminum line.
Claims14
A process for fabricating a semiconductor device, comprising the steps of:
- a) forming at least one lower metal line over a semiconductor substrate;
- b) covering said lower metal line with an inter-level insulating layer wherein said semiconductor substrate is heated to a temperature that is less than or equal to a first temperature, wherein said inter-level insulating layer is deposited at the first temperature;
- c) forming at least one via-hole in said inter-level insulating layer;
- d) performing out an outgassing process wherein said semiconductor substrate is heated to a second temperature that is equal to or less than said first temperature;
- and
- e) forming at least one upper metal line penetrating into said via-hole and formed of a conductive material selected from the group consisting of aluminum and aluminum alloys wherein said at least one upper metal line is formed in a vacuum deposition at a temperature that is lower than said first temperature.
3 more elements
Dependencies are inferred from the claim text.