Method and product for improved use of low k dielectric material among integrated circuit interconnect structures
AssigneeAdvanced Micro Devices, Inc.
InventorChristopher H. Raeder
Life of this patent
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Abstract
A method is presented for forming a liner upon spaced interconnect structures arranged upon a semiconductor topography. An oxide layer may be deposited to form the liner. The spaced interconnect structures may each include an interlevel dielectric portion arranged upon a metal interconnect portion, with gaps defined between adjacent interconnect structures. A low k dielectric material may be deposited over the interconnect structures such that the low k material substantially fills the gaps between adjacent interconnect structures. The low k dielectric material may then be planarized, preferably by chemical mechanical polishing.
Claims20
A method for forming an integrated circuit, comprising:
- forming a liner upon interconnect structures, each of which comprise an interlevel dielectric portion arranged upon a metal interconnect portion, wherein gaps are defined between adjacent interconnect structures spaced across a semiconductor topography;
- depositing a low k dielectric material over the interconnect structures such that the low k dielectric material substantially fills the gaps between adjacent interconnect structures;
- and
- planarizing the low k dielectric material, wherein said planarizing the low k dielectric material comprises polishing the low k dielectric material such that substantially all low k dielectric material is removed from directly above the interconnect structures.
A method for forming an integrated circuit, comprising:
- forming a layer of metal above a semiconductor topography;
- forming a layer of dielectric material upon the layer of metal;
- patterning the layer of dielectric material and the layer of metal to form spaced interconnect structures, wherein gaps are defined between adjacent interconnect structures, and wherein the interconnect structures each comprise a interlevel dielectric portion arranged upon a metal interconnect portion;
- forming a liner upon the interconnect structures and the semiconductor topography;
- depositing a low k dielectric material over the interconnect structures such that the low k dielectric material substantially fills the gaps between adjacent interconnect structures;
- and
- planarizing the low k dielectric material, wherein said planarizing the low k dielectric material comprises polishing the low k dielectric material such that substantially all low k dielectric material is removed from directly above the interconnect structures.
A method for forming an integrated circuit, comprising:
- forming a liner upon interconnect structures, each of which comprise an interlevel dielectric portion arranged upon a metal interconnect portion, wherein gaps are defined between adjacent interconnect structures spaced across a semiconductor topography;
- depositing a low k dielectric material over the interconnect structures such that the low k dielectric material substantially fills the gaps between adjacent interconnect structures;
- and
- planarizing the low k dielectric material, wherein said planarizing the low k dielectric material comprises polishing the low k dielectric material, wherein the spaced interconnect structures each further comprise a polish stop portion arranged upon the interlevel dielectric portion, and wherein said polishing the low k dielectric material is discontinued at a point in time subsequent to the initiation of removing of the polish stop portions.
A method for forming an integrated circuit, comprising:
- forming a layer of metal above a semiconductor topography;
- forming a layer of dielectric material upon the layer of metal;
- patterning the layer of dielectric material and the layer of metal to form spaced interconnect structures, wherein gaps are defined between adjacent interconnect structures, and wherein the interconnect structures each comprise a interlevel dielectric portion arranged upon a metal interconnect portion;
- subsequently forming a liner upon the interconnect structures and the semiconductor topography;
- depositing a low k dielectric material over the interconnect structures such that the low k dielectric material substantially fills the gaps between adjacent interconnect structures, wherein said depositing a low k dielectric material comprises depositing fluorine-doped silicon dioxide over the interconnect structures;
- and
- planarizing the low k dielectric material.
Dependencies are inferred from the claim text.