Simplified process for defining the tunnel area in non-aligned, non-volatile semiconductor memory cells

In a memory matrix that has associated control circuitry, a process to define a tunnel area in non-DSCP, non-volatile memory cells having semi-conductive floating gates which are non-aligned, each memory cell being associated with a respective selection transistor, the process comprising at least the following phases:

• forming a gate dielectric layer on a semiconductor substrate for one of the selection transistors and for its associated memory cell;
• using a tunnel mask to define the tunnel area that extends from an area on which a control gate of the one selection transistor will be formed to an area on which will be formed a floating gate of the memory cell associated with the one selection transistor;
• etching the gate dielectric layer in all of the tunnel area to a surface of the semiconductor substrate;
• growing a tunnel oxide layer on the surface of the semiconductor substrate in the tunnel area;
• forming a floating gate for the memory cell associated with the one selection transistor with at least a portion of the floating gate disposed over the tunnel oxide;
• and
• using the tunnel oxide to form a gate oxide under the control gate of the related selection transistor.