Low dielectric constant stop layer for integrated circuit interconnects
AssigneeAdvanced Micro Devices, Inc.
InventorsMinh Van Ngo, Christy Mei-Chu Woo
Life of this patent
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Abstract
An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device and a device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has a channel opening and a conductor core filling the channel opening. A via stop layer is formed over the channel dielectric layer to have a hydrogen concentration below 15 atomic % and a via dielectric layer is formed over the via stop layer and has a via opening. A second channel dielectric layer over the via dielectric layer has a second channel opening. A second conductor core, filling the second channel opening and the via opening, is connected to the semiconductor device.
Claims6
An integrated circuit comprising:
- a semiconductor substrate having a semiconductor device provided thereon;
- first dielectric layer formed over the semiconductor substrate having an opening provided therein;
- a conductor core filling the opening and connected to the semiconductor device;
- a via stop layer formed over the first dielectric layer and the conductor core, the stop layer having a hydrogen concentration below 15 atomic %, wherein the via stop layer is deposited to a thickness whereby the capacitive coupling is reduced over 50% over a stop layer having a hydrogen concentration over 15 atomic %;
- a via dielectric layer formed over the via stop layer and having a via opening provided therein open to the conductor core;
- a second dielectric layer formed over the via dielectric layer and having a second opening provided therein open to the via opening;
- and
- a second conductor core filling the via and second openings and connected to the conductor core.
An integrated circuit comprising:
- a semiconductor substrate having a semiconductor device provided thereon;
- a device dielectric layer formed on the semiconductor substrate;
- a first channel stop layer formed over the device dielectric layer;
- a first channel dielectric layer formed on the device dielectric layer having a first channel opening provided therein;
- a first conductor core filling the first channel opening and connected to the semiconductor device;
- a via stop layer formed over the first channel dielectric layer and the first conductor core, the via stop layer having a hydrogen concentration below 15 atomic %;
- a via dielectric layer formed over the via stop layer and having a via opening provided therein open to the conductor core;
- a second channel stop layer formed over the via dielectric layer, the second channel stop layer having a hydrogen concentration below 15 atomic %, wherein the via and the second channel stop layers are deposited to thicknesses whereby the capacitive couplings are reduced over 50% over stop layers having a hydrogen concentration over 15 atomic %;
- a second channel dielectric layer formed over the second channel stop layer and having a second channel opening provided therein open to the via opening;
- and
- a second conductor core filling the via and second channel openings and connected to the first conductor core.
Dependencies are inferred from the claim text.