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US 6,441,448 B1Granted
Semiconductor storage device
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsShigenobu Maeda, Yasuo Yamaguchi, Hirotada Kuriyama
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Abstract
A memory cell which is capable of reducing the memory cell size in SRAM using a field-shield isolation on an SOI substrate. An isolation oxide film is provided between a field-shield isolation plate for n-type transistors and a field-shield isolation plate for p-type transistors.
Claims4
A semiconductor storage device having a memory cell including device isolation, comprising:
- a first driver transistor;
- a second driver transistor;
- a first and a second load transistors that form a flip-flop circuit together with said first and said second driver transistors;
- a first access transistor connected to a drain active region of said first driver transistor and a drain active region of said first load transistor;
- a second access transistor connected to a drain active region of said second driver transistor and a drain active region of said second load transistor;
- wherein said device isolation in said memory cell includes field-shield isolation, the field-shield isolation is located between said first access transistor and said second access transistor, and between the drain active region of said first driver transistor and the drain active region of said second driver transistor, and between the drain active region of said first load transistor and the drain active region of said second load transistor;
- and oxide film isolation, the oxide film isolation is located between the drain active region of said first driver transistor and the drain active region of said first load transistor, and between the drain active region of said second driver transistor and the drain active region of said second load transistor, is in contact with each drain active region.
4 more elements
A semiconductor storage device having a memory cell including device isolation, comprising:
- a first driver transistor;
- a second driver transistor;
- a first and a second load transistors that form a flip-flop circuit together with said first and said second driver transistors;
- a first access transistor connected to a drain active region of said first driver transistor and a drain active region of said first load transistor;
- and
- a second access transistor connected to a drain active region of said second driver transistor and a drain active region of said second load transistor,
- wherein
- said device isolation in said memory cell includes field-shield isolation,
- active regions of said first access transistor and the drain active region of said first driver transistor are isolated from each other by a first field-shield isolation and connected to each other via an interconnection, and
- active regions of said second access transistor and the drain active region of said second driver transistor are isolated from each other by a second field-shield isolation and connected to each other via an interconnection, the first field-shield isolation and the second field shield isolation are a continuous and integrated pattern.
7 more elements
Dependencies are inferred from the claim text.