Embedded type flash memory structure and method for operating the same

An embedded type flash memory structure, comprising:

• a semiconductor substrate;
• a first deep doped-region formed on the surface of said semiconductor substrate;
• a plurality of first shallow doped-regions formed in said first deep doped-region, wherein a first plurality of said plurality of first shallow doped-regions constitute transistor sources and a second plurality of first shallow doped-regions constitute transistor drains and wherein an ion penetration depth of said first deep doped-region is greater than that of said first shallow doped-regions;
• a plurality of second shallow doped-regions formed in said first deep doped-region wherein each of said plurality of second shallow doped-regions surrounds a corresponding one of said first shallow doped-regions, wherein said corresponding one of said first shallow doped-regions is one of said transistor drains, wherein each of said transistor sources is excluded from being surrounded by one of said plurality of second shallow doped-regions and wherein an ion penetration depth of said plurality of second shallow doped-regions is greater than that of said plurality of first shallow doped-regions and less than said penetration depth of said first deep doped-region;
• a dielectric insulating layer stacked above said first deep doped-region;
• and
• a poly-silicon layer constituting a gate formed on the surface of said dielectric insulating layer, wherein said gate mutually and simultaneously controls the electric field between a plurality of said transistor sources and a corresponding plurality of said transistor drains.