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US 6,441,422 B1Granted
Structure and method for ultra-scalable hybrid DRAM cell with contacted P-well
AssigneeInternational Business Machines Corporation
InventorsJack A. Mandelman, Ramachandra Divakaruni, Carl J. Radens, Jai-hoon Sim
Life of this patent
Estimating the term…
Abstract
An ultra-scalable hybrid memory cell having a low junction leakage and a process of fabricating the same are provided. The ultra-scalable hybrid memory cell contains a conductive connection to the body region therefore avoiding isolation of the P-well due to cut-off by the buried strap outdiffusion region. The ultra-scalable hybrid memory cell avoids the above by using a shallower than normal isolation region that allows the P-well to remain connected to the body of the memory cell.
Claims14
A memory cell array comprising:
- a pluraity of vertical memory cells which are arranged in rows and columns, each vertical memory cell being located in a storage trench that is present in a P-well of a Si-containing substrate and each vertical memory cell includes a MIOSFET region which comprises at least a gate oxide formed over a storage capacitor, said MOSFET region and said storage capacitor being electrically connected by a one-sided buried-strap outdifision region, said one-sided buried-strap outdiffision region being confined to a substanfally center portion of the storage trench, wherein the one-sided buried-strap outdiffusion region and the gate oxide lie within a common aperture that is located on a single side of the storage trench, and
- shallow isolation trench regions located between adjacent columns of memory cells so as to separate columns of memory cells, each of said shallow isolation trench regions having a depth that is substantially above said one-sided buried-strap outdiffusion region thereby not cutting into said one-sided buried-strap outdiffiusion region, yet being deep enough to isolate adjacent bitline diffusion regions that abut each vertical DRAM cell.
Dependencies are inferred from the claim text.