US 6,440,818 B1 · Method of reducing leakage current of a semiconductor wafer

Abstract

A semiconductor wafer includes a silicon substrate, an active area positioned on the silicon substrate, and a field oxide layer positioned on the surface of the silicon substrate surrounding the active area. The present invention forms a doped area in the silicon substrate and within the active area and then deposits a dielectric layer on the surface of the semiconductor wafer. A dry etching process is performed to remove the dielectric layer. The top power of the dry etching process ranges between three hundred and five hundred watts to prevent damage to the silicon substrate near the field oxide layer and within the active area by the dry etching process, and to reduce the leakage current of the doped area. Additionally, the present invention also uses a wet etching process to remove the dielectric layer, which prevents an anisotropic physical impact on the silicon substrate near the field oxide layer to reduce the leakage current of the doped area.

Claims19

Dependent claims

A method of reducing leakage current of a semiconductor wafer, the semiconductor wafer comprising a silicon substrate, an active area positioned on the silicon substrate, and a field oxide (FOX) layer positioned on the silicon substrate surrounding the active area, the method comprising:

forming a doped area in the silicon substrate within the active area;
depositing a dielectric layer on the semiconductor wafer;
performing a dry etching process to remove at least a portion of the dielectric layer to expose the surface of the silicon substrate in the active area, and ranging the top power of the dry etching process to between three hundred and five hundred watts;
and
performing a self-aligned silicide (salicide) process to form a self-aligned silicide layer on the surface of the doped area;
wherein the top power range defined in the dry etching process prevents the dry etching process from destroying the silicon substrate adjacent to the field oxide layer and within the active area, and hence reduces leakage current of the doped area.

3 more elements

A method of reducing leakage current of a semiconductor wafer, the semiconductor wafer comprising a silicon substrate, at least one active area positioned in a region of the silicon substrate, and a FOX layer positioned on the surface of the silicon substrate, the FOX layer comprising a bird's beak structure surrounding the active area, the method comprising:

forming a doped area in the silicon substrate within the active area;
depositing a dielectric layer on the semiconductor wafer;
performing a photolithographic process to define a predetermined region of a self-aligned silicide (salicide) layer utilizing a salicide block (SAB) mask;
performing a dry etching process to etch the dielectric layer to a predetermined height;
performing a wet etching process to remove the remaining dielectric layer in the predetermined region to expose the surface of the silicon substrate;
and
performing a salicide process to form a salicide layer on the surface of the predetermined region;
wherein the dry etching process reduces the reaction time of the wet etching process, and the wet etching process prevents an anisotropic physical impact on the bird's beak structure and on the silicon substrate neighboring the bird's beak structure, which prevents sinking of the salicide layer near the bird's beak structure, and hence reduces leakage current of the doped area.

5 more elements

Dependencies are inferred from the claim text.

Method of reducing leakage current of a semiconductor wafer

Life of this patent

Method of reducing leakage current of a semiconductor wafer

Life of this patent

Abstract

Claims19