Method of fabricating a poly-poly capacitor with a SiGe BiCMOS integration scheme
AssigneeInternational Business Machines Corporation
InventorsDouglas Duane Coolbaugh, James Stuart Dunn, Stephen Arthur St. Onge
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Abstract
A method for fabricating a poly-poly capacitor integrated with a BiCMOS process which includes forming a lower plate electrode of a poly-poly capacitor during deposition of a gate electrode of a CMOS transistor; and forming an upper SiGe plate electrode during growth of a SiGe base region of a heterojunction bipolar transistor.
Claims18
A method for fabricating a poly-poly capacitor integrated with a BiCMOS process comprising forming a lower plate electrode of a poly-poly capacitor during deposition of a gate electrode of a CMOS transistor, and forming an upper SiGe plate electrode of said poly-poly capacitor during growth of a SiGe base region of a heterojunction bipolar transistor.
A method for fabricating a poly-poly capacitor integrated with a BiCMOS process comprising the steps of:
- (a) forming a first polysilicon layer over a portion of an isolation region in a device region in which a poly-poly capacitor is to be formed, and in a CMOS transistor device region, said first polysilicon layer in said CMOS transistor device region comprises a gate electrode of said CMOS transistor;
- (b) forming fist nitride spacers about said first polysilicon layer in said poly-poly capacitor device region;
- (c) depositing a nitride layer over said first polysilicon layer and said fist nitride spacers in said poly-poly capacitor device region;
- (d) implanting ions of a first conductivity type into said first polysilicon layer so as to form a lower electrode of said poly-poly capacitor,
- (e) removing portions of said nitride layer so as to film second nitride spacers and to expose a portion of said lower electrode;
- (f) forming a film stack on at least said exposed portion of said lower electrode, said film stack comprising an oxide layer, a second layer of polysilicon and a layer of SiGe;
- (g) implanting ions of a second conductivity type that are different from said fist conductivity type into said layer of SiGe and said second layer of polysilicon;
- (h) etching at least said layer of SiGe and said second layer of polysilicon so as to form an upper electrode of said poly-poly capacitor, and
- (i) saliciding all exposed surfaces of said upper electrode.
A method for fabricating a poly-poly capacitor integrated with a BiCMOS process comprising the steps of:
- (a) forming a first polysilicon layer over a portion of an isolation region in a device region in which a poly-poly capacitor is to be formed and in a CMOS transistor device region, said first polysilicon layer in said CMOS transistor device region comprises a gate electrode of said CMOS transistor;
- (b) forming first nitride spacers about said first polysilicon layer in said poly-poly capacitor device region;
- (c) depositing a nitride layer over said first polysilicon layer and said first nitride spacers layer in said poly-poly capacitor device region;
- (d) implanting ions of a first conductivity type into said first polysilicon layer so as to form a lower electrode of said poly-poly capacitor;
- (e) forming a film stack on at least said nitride layer, said film stack comprising an oxide layer, a second layer of polysilicon and a layer of SiGe;
- (f) implanting ions of a second conductivity type that are different from said first conductivity type into said layer of SiGe and said second layer of polysilicon;
- (g) etching at least said layer of SiGe and said second layer of polysilicon so as to form an upper electrode of said poly-poly capacitor;
- and
- (h) saliciding all exposed surfaces of said upper electrode.
Dependencies are inferred from the claim text.