Damascene-gate process for the fabrication of MOSFET devices with minimum poly-gate depletion, silicided source and drain junctions, and low sheet resistance gate-poly

A process of fabricating a sub-0.1 μm MOSFET device having minimum poly depletion, silicided source and drain junctions and very low sheet resistance poly-gates comprising the steps of:

• (a) providing a dummy gate region on a surface of a semiconductor substrate, said dummy gate region including polysilicon sandwiched between a bottom oxide layer and a top oxide layer;
• (b) forming activated source and drain regions in said semiconductor substrate using said dummy gate region as an implantation mask;
• (c) siliciding the surface of said semiconductor substrate overlying said activated source and drain regions;
• (d) forming an insulator layer on said surface of said semiconductor substrate, said insulator layer also surrounding said dummy gate region;
• (e) planarizing said insulator layer so as to remove said top oxide layer of said dummy gate region thus exposing said polysilicon;
• (f) selectively removing said polysilicon and said bottom oxide layer of said dummy gate region so as to provide an opening which exposes a portion of said semiconductor substrate;
• (g) forming a gate dielectric on said exposed portion of said semiconductor substrate;
• (h) depositing a gate conductor on said gate dielectric;
• and
• (i) etching said insulator layer formed in step (d).