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US 6,440,800 B1Granted
Method to form a vertical transistor by selective epitaxial growth and delta doped silicon layers
AssigneeChartered Semiconductor Manufacturing Ltd.
InventorsJames Yong Meng Lee, Ying Keung Leung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Lap Chan, Elgin Quek, Ravi Sundaresan, Yang Pan
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Abstract
A method for a vertical transistor by selective epi deposition to form the conductive source, drain, and channel layers. The conductive source, drain, and channel layers are preferably formed by a selective epi process. Dielectric masks define the conductive layers and make areas to form vertical contacts to the conductive S/D and channel layers.
Claims12
A method of fabrication of vertical transistor;
- comprising the steps of:
- a) forming a pad layer and a first insulating layer over a substrate;
- b) forming a transistor opening through said pad layer and said first insulating layer;
- c) forming a first conductive layer over said substrate in said transistor opening;
- said first conductive layer having a first conductivity type;
- d) forming a first dielectric layer over portions of said first conductive layer and over said first insulating layer;
- e) forming a second conductive layer over the exposed portions of said first conductive layer;
- said second conductive layer having a second conductivity type;
- f) forming a second dielectric layer over portions of said second conductive layer and over said first insulating layer;
- g) forming a third conductive layer over the exposed portions of said second conductive layer;
- said third conductive layer having a first conductivity type;
- h) forming a third dielectric layer over said second dielectric layer and said third conductive layer;
- i) forming a trench through said third conductive layer said third, second and first conductive layers to at least expose said substrate;
- j) forming a gate dielectric layer on the sidewalls and bottom of said trench,
- k) forming a gate over said gate dielectric layer and filling said trench;
- and
- l) forming a cap dielectric layer over said third dielectric layer;
- and
- m) forming contacts through said first second and third dielectric layers to contact said first, second and third conductive layers.
16 more elements
A method of fabrication of vertical transistor;
- comprising the steps of:
- a) forming a pad layer and an first insulating layer over a substrate;
- (1) said pad layer comprised of silicon oxide and said first insulating layer comprised of silicon nitride having a thickness of between about 1000 and 5000 Å;
- b) forming a transistor opening through said pad layer and said first insulating layer;
- c) forming a first conductive layer using a selective epitaxial process over said substrate in said transistor opening;
- said first conductive layer having a first conductivity type;
- d) forming a first dielectric layer over portions of said first conductive layer and over said first insulating layer;
- (1) said first dielectric layer is comprised of silicon oxide;
- e) forming a second conductive layer over the exposed portions of said first conductive layer;
- said second conductive layer having a second conductivity type;
- (1) said second conductive layer formed by a selective epitaxial process and said second conductive layer is comprised of silicon;
- f) forming a second dielectric layer over portions of said second conductive layer and over said first insulating layer;
- (1) said second dielectric layer is comprised of silicon oxide;
- g) forming a third conductive layer over the exposed portions of said second conductive layer using a selective epitaxial process;
- said third conductive layer having a first conductivity type;
- h) forming a third dielectric layer (38) over said second dielectric layer and said third conductive layer;
- i) forming a trench through said third conductive layer said third, second and first conductive layers to at least expose said substrate;
- (1) said trench has a width of between about 0.2 μm and 2.0 μm;
- j) forming a gate dielectric layer on the sidewalls and bottom of said trench,
- (1) said gate dielectric layer is comprised of silicon oxide;
- k) forming a gate over said gate dielectric layer and filling said trench;
- (1) said gate comprised of polysilicon or tungsten (W);
- said gate formed by depositing a gate layer over filling said trench and over said third, second and first dielectric layers and chemical-mechanical polishing (CMP) said gate material layer;
- l) forming a cap dielectric layer over said third dielectric layer;
- m) forming contacts through said cap dielectric, first, second, and third dielectric layers to contact said first, second and third conductive layers.
22 more elements
Dependencies are inferred from the claim text.