Method for forming an array of DRAM cells by employing a self-aligned adjacent node isolation technique

Abstract

In a method for forming an array of dynamic random access memory (DRAM) cells, each DRAM cell having one or more field effect transistors (FETs) and a deep trench capacitor, first, a substrate is prepared. Line type active areas (AAs) are patterned on the substrate to thereby provide AA lines (AALs). Next, deep trench capacitors (DTCs) are fabricated in an AAL in a predetermined configuration to thereby define deep trench areas (DTAs) for the DTCs, each DTC having a storage node, a collar insulator and a buried strap. In subsequent step, a node isolation area (NIA) is defined to isolate a storage node of a DTC and a storage node of its adjacent DTC and then a trench isolation area (TIA) for each of the DRAM cell is defined. Further, one or more FETs are fabricated in each AA to thereby form the array of DRAM cells, wherein a conductive path is formed from an electrode of one of the FETs to the buried strap of a corresponding DTC. In accordance with the present invention, since the AAs can be formed before DTCs are formed, the so-called thermal budget problem can be solved or relaxed; the AAs can be patterned with a great ease since the AAs are patterned as a line type; and the overlay margin between each AA and a corresponding DTA in a DRAM cell can be improved by employing a maskless self-aligned adjacent node isolation technique.

Dependencies are inferred from the claim text.