Split-gate vertically oriented EEPROM device and process

A semiconductor device comprising:

• a semiconductor substrate having a source region therein;
• a vertically disposed channel region overlying the source region;
• a select gate electrode overlying the semiconductor substrate adjacent to the vertically disposed channel region;
• a dielectric layer overlying the semiconductor substrate and the vertically disposed channel region and separating the select gate electrode therefrom;
• a floating gate electrode overlying the select gate electrode and surrounding a portion of the vertically disposed channel region;
• and
• a control gate electrode overlying the select gate electrode and surrounding the floating gate electrode,
• wherein the control gate electrode controls an electrical charge state of the floating gate electrode, and
• wherein the select gate electrode regulates flow of electrical charge into the vertically disposed channel region from the semiconductor substrate.

A semiconductor device comprising:

• a substrate;
• a first transistor overlying the substrate, the first transistor having a first current electrode overlying a second current electrode wherein the first and second current electrodes are separated bye a channel region, a floating gate electrode laterally adjacent the channel region, and a control gate electrode laterally adjacent the floating gate electrode;
• and
• a second transistor overlying the first transistor and being serially coupled to the first transistor, the second transistor having a first current electrode overlying a second current electrode, a channel region separating the first and second current electrodes, and a select gate electrode laterally adjacent the channel region, wherein the first transistor is a floating gate storage transistor for storing a logic bit value and the second transistor is a select gate for selecting the first transistor.

A semiconductor device comprising:

• a substrate;
• a first transistor overlying the substrate, the first transistor having a first current electrode underlying a channel region, and a select gate electrode laterally adjacent the channel region;
• and
• a second transistor overlying the first transistor and being serially coupled to the first transistor, the second transistor having a second current electrode overlying the channel region wherein the first and second current electrodes are separated by the channel region, a floating gate electrode adjacent the channel region, wherein the floating gate electrode is further characterized as a spacer which surrounds the channel region of the second transistor, and wherein the channel region of the second transistor is a cylindrical region and a control gate electrode laterally adjacent the floating gate electrode, wherein the second transistor is a floating gate storage transistor for storing a logic bit value and the first transistor is a select gate for selecting the second transistor.

A method for forming a semiconductor device comprising the steps of:

• providing a diffusion region which is made of a material capable of selective growth;
• growing a first current electrode vertically from the diffusion region;
• growing a first channel region portion vertically from the first current electrode;
• growing a second channel region portion vertically from the first channel region portion;
• forming a third current electrode coupled to the second channel region;
• forming a floating gate electrode laterally adjacent a first selected region selected from a group consisting of:
• the first channel region portion and the second channel region portion;
• forming a select gate electrode laterally adjacent a second selected region selected from a group consisting of:
• the first channel region portion and the second channel region portion, wherein the second selected region is different from the first selected region;
• and
• forming a control gate electrode laterally adjacent the floating gate electrode.

A method for forming a semiconductor device comprising the steps of:

• providing a substrate;
• forming a vertically-oriented conductive region overlying and contacted to the substrate, the vertically-oriented conductive region having a first current electrode at a bottom portion of the vertically-oriented conductive region, a first channel region portion overlying the first current electrode, a second channel region portion overlying the first channel region portion, and a second current electrode overlying the second channel region portion;
• forming a select gate electrode laterally adjacent the second channel region portion;
• forming a floating gate electrode laterally adjacent the first channel region portion;
• and
• forming a control electrode adjacent the floating gate. electrode.

A method for forming a semiconductor device comprising the steps of:

• providing a substrate having a top surface;
• forming a vertically-oriented channel region wherein current flows through the vertically-oriented channel region perpendicular to the top surface of the substrate;
• forming a thermally grown oxide layer laterally adjacent the vertically-oriented channel region, the thermally grown oxide layer having micropores therethrough;
• forming a deposited dielectric layer laterally adjacent the thermally grown oxide layer wherein the deposited dielectric layer has micropores misaligned to the thermally grown oxide layer;
• exposing the deposited dielectric layer to a dopant species to dope one of either the thermally grown oxide layer or the deposited dielectric layer with a species selected from the group consisting of:
• nitrogen and fluorine;
• and
• forming a gate electrode laterally adjacent the deposited dielectric layer.

A method for forming a semiconductor device comprising the steps of:

• forming a plurality of source electrode diffusion regions with dopant atoms of a first conductivity type within a substrate, the plurality of source electrode diffusion regions being separated from each other by disconnection regions wherein the disconnection regions are doped with dopant atoms of an second conductivity type wherein the second conductivity type is opposite the first conductivity type;
• forming a gate electrode overlying the disconnection regions, the gate electrode being one gate electrode in a memory cell structure;
• selectively enabling the gate electrode to selectively couple together the plurality of source electrode diffusion regions in the plurality of source electrode diffusion regions via inversion regions formed within the disconnection regions, wherein the inversion regions are regions of the first conductivity type formed via enablement of the gate electrode;
• and
• transmitting an electrical voltage signal through all of the inversion regions and the plurality of source electrode diffusion regions.

A method for forming a semiconductor device comprising the steps of:

• providing a silicon diffusion region which is made of a material capable of selective growth;
• growing a first current electrode vertically from the silicon diffusion region, the first current electrode being of a first conductivity type;
• growing a first channel region portion vertically from the first current electrode, the first channel region being of a second conductivity type which is opposite the first conductivity type;
• growing a second channel region portion vertically from the first channel region portion;
• forming a third current electrode coupled to the second channel region portion, the third current electrode being of the first conductivity type;
• forming a floating gate electrode laterally adjacent a first selected region selected from a group consisting of:
• the first channel region portion and the second channel region portion;
• forming a select gate electrode laterally adjacent a second selected region selected from a group consisting of:
• the first channel region portion and the second channel region portion, wherein the second selected region is different from the first selected region;
• and
• forming a control gate electrode laterally adjacent the floating gate electrode.