Current-controlled CMOS logic family
AssigneeBroadcom Corporation
InventorArmond Hairapetian
Life of this patent
Estimating the term…
Abstract
Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.
Claims17
A metal-oxide-semiconductor field-effect transistor (MOSFET) circuit fabricated on a silicon substrate, comprising:
- first circuitry implemented using current-controlled complementary metal-oxide semiconductor C3MOS logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals, the first circuitry being configured to process a first signal having a first frequency;
- and
- second circuitry implemented using conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current is dissipated, the second circuitry being coupled to the first circuitry and configured to process a second signal having a second frequency that is different than the first frequency,
- wherein the first circuitry comprises an input circuit that is implemented using the C3MOS logic, and is configured to deserialize the first signal into a plurality of lower frequency signals.
A metal-oxide-semiconductor field-effect transistor (MOSFET) circuit comprising:
- a first circuit implemented using current-controlled complementary metal-oxide semiconductor (C3MOS) logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals, the first circuit being configured to receive an input signal having a first frequency and to generate a first output signal having a second frequency lower than the first frequency;
- a second circuit coupled to the first circuit and implemented using conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current is dissipated, the second circuit being configured to receive and process the first output signal and to generate a second output signal;
- and
- a third circuit coupled to the second circuit and implemented using C3MOS logic, the third circuit being configured to receive and process the second output signal and to generate a third output signal.
A method for processing high speed signals using silicon complementary metal-oxide-semiconductor (CMOS) technology, the method comprising:
- receiving the high speed signal at a first circuit that uses current-controlled complementary metal-oxide semiconductor (C3MOS) logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals;
- deserializing the high speed signal into a plurality of lower frequency signals;
- processing the plurality of lower frequency signals by a second circuit that uses standard CMOS logic wherein substantially zero static current is dissipated;
- and
- serializing output signals of the second circuit by a third circuit that uses C3MOS logic.
A metal-oxide-semiconductor field-effect transistor (MOSFET) circuit fabricated on a silicon substrate, comprising:
- first circuitry implemented using current-controlled complementary metal-oxide semiconductor C3MOS logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals, the first circuitry being configured to process a first signal having a first frequency;
- and
- second circuitry implemented using conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current is dissipated, the second circuitry being coupled to the first circuitry and configured to process a plurality of second signals having a second frequency that is lower than the first frequency,
- wherein the first circuitry comprises an output circuit that is implemented using the C3MOS logic, and is configured to serialize the second plurality of signals into a single output signal.
Dependencies are inferred from the claim text.