Integrated verification and manufacturability tool

A method comprising:

• importing an integrated device layout into a common hierarchical database to create shared data;
• executing a sequence of program instructions that initiate the operation of one or more checking components that perform layout verification operations on the shared data;
• and
• executing a sequence of program instructions that initiate the operation of a distinct optical process correction component that performs optical process correction (OPC) operations on the shared data.

A machine-readable medium having stored thereon sequences of instructions that, when executed, cause one or more electronic systems to:

• import an integrated device layout to a common hierarchical database to create shared data;
• initiate the operation of one or more checking components that perform layout verification operations on the integrated device design on the shared data;
• and
• initiate the operation of a distinct optical process correction component that performs optical process correction (OPC) operations on the shared data.

An electronic data signal embodied in a data communications medium shared among a plurality of network devices comprising sequences of instructions that, when executed, cause one or more electronic systems to:

• import an integrated device layout into a hierarchical database;
• initiate the operation of one or more checking components that perform layout verification operations on the integrated device design;
• and
• initiate the operation of a distinct software component that performs optical process correction (OPC) operations on the integrated device design.

A machine readable medium on which is stored a sequence of programmed instructions to be executed by one or more processors in order to:

• create a shared hierarchical database that represents components of an integrated circuit layout having a number of hierarchy layers, wherein redundant patterns of edges and/or polygons are described in the hierarchical database along with indication of where each such redundant pattern is found in the integrated circuit layout;
• selectively promote edges or polygons in the database that interact to another layer of hierarchy such that each placement of the interacting edges or polygons can be separately analyzed;
• and
• initiating a number of checking components and a distinct optical process correction component that analyze the data in the shared hierarchical database to ensure the manufacturability of the integrated circuit layout.