Gate-coupled ESD protection circuit without transient leakage
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMing-Dou Ker, Chen-Chia Wang, Hun-Hsien Chang
Life of this patent
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Abstract
An apparatus of preventing integrated circuits from interfering by electrostatic-discharge (ESD), applied in an internal circuit and an input pad, both coupled with a first power line and a second power line, comprises a voltage clamp circuit and a voltage bias circuit. The voltage clamp circuit, with a transistor, connects to the second power line for clamping potential level through the voltage clamp circuit. The voltage bias circuit, with at least one diode coupled in series, connects to the voltage clamp circuit and the first power line for biasing the voltage clamp circuit to the second power line.
Claims21
An apparatus of preventing integrated circuits from interfering by electrostatic-discharge (ESD), wherein said apparatus comprises:
- an internal circuit coupled with said first power line and said second power line;
- an input pad coupled to said internal circuit for inputting signals to said internal circuit;
- a first voltage bias circuit coupled to said first power line for biasing said first voltage bias circuit to said second power line, comprising at least one diode coupled in series, and said at least one diode comprises a first serial diode, wherein an anode of said first serial diode is coupled to said input pad, and a cathode of said first serial diode is coupled to said first power line;
- a first voltage clamp circuit coupled to said second power line for clamping potential level through said first voltage clamp circuit, comprising a first transistor device, wherein a source of said first transistor device coupled to said second power line, and a drain of said first transistor device coupled to said anode of said first serial diode;
- a second voltage bias circuit coupled to said second power line for biasing said first voltage bias circuit to said first power line;
- and
- a second voltage clamp circuit coupled to said second voltage bias circuit and said first power line for clamping potential level through said second voltage clamp circuit.
An apparatus of preventing integrated circuits from interfering by electrostatic-discharge (ESD), connected between an internal circuit and an input pad, said internal circuit coupled to a first power line and a second power line, said input pad inputting signals to said internal circuit, said apparatus comprising:
- a first transistor device, wherein a source of said first transistor device coupled to said second power line, and a drain of said first transistor device coupled to said input pad;
- a voltage clamp circuit, coupled to a second power line for clamping voltage level of a gate of said first transistor device;
- and
- a voltage bias circuit, comprising a first diode and a voltage bias circuit subassembly, wherein a cathode of said first diode coupled to said first power line, an anode of said first diode coupled to a first end of said voltage bias circuit subassembly and said voltage clamp circuit, and a second end of said voltage bias circuit subassembly coupled to said drain of said first transistor device for substantially preventing the overshooting inputting signals triggering said first transistor device.
An apparatus of preventing integrated circuits from interfering by electrostatic-discharge (ESD), connected between an internal circuit and an input pad, said internal circuit coupled to a first power line and a second power line, said input pad inputting signals to said internal circuit, said apparatus comprising:
- a first transistor device, wherein a source of said first transistor device coupled to said second power line, and a drain of said first transistor device coupled to said input pad;
- a first voltage clamp circuit, coupled to a second power line for clamping voltage level of a gate of said first transistor device;
- a first voltage bias circuit, comprising a first diode and a first voltage bias circuit subassembly, wherein a cathode of said first diode coupled to said first power line, an anode of said first diode coupled to a first end of said first voltage bias circuit subassembly and said first voltage clamp circuit, and a second end of said first voltage bias circuit subassembly coupled to said drain of said first transistor device for substantially preventing the overshooting inputting signals triggering said first transistor device;
- a second transistor device, wherein a source of said second transistor device coupled to said first power line, and a drain of said second transistor device coupled to said input pad;
- a second voltage clamp circuit, coupled to a first power line for clamping voltage level of a gate of said second transistor device;
- and
- a second voltage bias circuit, comprising a second diode and a second voltage bias circuit subassembly, wherein an anode of said second diode coupled to said second power line, a cathode of said second diode coupled to a first end of said second voltage bias circuit subassembly and said second voltage clamp circuit, and a second end of said second voltage bias circuit subassembly coupled to said drain of said second transistor device for substantially preventing the undershooting inputting signals triggering said first transistor device.
Dependencies are inferred from the claim text.