Semiconductor device capable of reducing noise

A semiconductor device formed in a main surface of a semiconductor substrate, comprising:

• a first internal circuit formed in a first region of said main surface of said semiconductor substrate and including a first N channel MOS transistor and a first P channel MOS transistor;
• a second internal circuit formed in a second region of said main surface of said semiconductor substrate and including a second N channel MOS transistor and a second P channel MOS transistor;
• and
• an interface circuit formed in an interface circuit region of said main surface of said semiconductor substrate, including a third N channel MOS transistor and a third P channel MOS transistor, and transmitting a signal between said first internal circuit and said second internal circuit,
• said first region including a first N well for said first P channel MOS transistor, and a first P well for said first N channel MOS transistor, said second region including a second N well for said second P channel MOS transistor, and a second P well for said second N channel MOS transistor, and said interface circuit region including a third N well for said third P channel MOS transistor, and a third P well for said third N channel MOS transistor.

A semiconductor device including one semiconductor chip, comprising:

• first, second and third high potential power supply terminals formed on said semiconductor chip and receiving power supply voltages applied from an exterior to the semiconductor chip;
• first, second and third low potential power supply terminals formed on said semiconductor chip and receiving power supply potentials respectively lower than potentials of said first, second and third high potential power supply terminals applied from an exterior to the semiconductor chip;
• a first internal circuit supplied with operating power supply voltages from said first high potential power supply terminal and said first low potential power supply terminal;
• a second internal circuit supplied with operating power supply voltages from said second high potential power supply terminal and said second low potential power supply terminal;
• and
• an interface circuit supplied with operating power supply voltages from said third high potential power supply terminal and said third low potential power supply terminal, said interface circuit including a first transmission portion receiving a first signal from said first internal circuit and outputting a second signal to said second internal circuit, and a second transmission portion receiving a third signal from said second internal circuit and outputting a fourth signal to said first internal circuit.