Single deposition layer metal dynamic random access memory

A memory comprising a semiconductor die having at least 224 single-bit memory cells, the die having signal and power interconnect consisting essentially of:

• a single deposition layer of highly conductive interconnect material;
• the single deposition layer of highly conductive interconnect material forming a plurality of bonding pads and serving to selectively interconnect the bonding pads, portions of a plurality of memory cells, a plurality of row address decoders, a plurality of column address decoders, and a plurality of sense amplifiers;
• at least one semiconductor interconnect layer interconnecting selected portions of the memory cells, the plurality of row address decoders, the plurality of column address decoders and the plurality of sense amplifiers;
• the single deposition layer of highly conductive interconnect material having a sheet resistance of less than one ohm per square;
• and
• the at least one semiconductor interconnect layer having a sheet resistance of greater than one ohm per square.

A memory, comprising:

• a semiconductor die having at least 224 single-bit memory cells and sized to fit within an industry standard package, the package having a maximum width of approximately 300 mils and a maximum length of approximately 675 mils, the die consisting essentially of:
• a substrate
• layers of non-interconnect circuity on the substrate;
• a single highly conductive interconnect layer having a sheet resistance of less than one ohm per square interconnecting portions of a plurality of the single-bit memory cells, portions of a plurality of signal bonding pads, portions of a plurality of power bonding pads, portions of a plurality of row address decoders, portions of a plurality of column address decoders, and portions of a plurality of sense amplifiers;
• and
• at least one semiconductor interconnect layer interconnecting other portions of the single-bit memory cells, other portions of the plurality of row address decoders, other portions of the plurality of column address decoders and other portions of the sense amplifiers.

A memory, comprising:

• a semiconductor die having at least 224 single-bit memory cells and sized to fit within an industry standard package, the package having a maximum width of approximately 300 mils and a maximum length of approximately 675 mils, the die having layers of interconnection circuity consisting of:
• a single highly conductive interconnect layer having a sheet resistance of less than one ohm per square interconnecting portions of a plurality of the single-bit memory cells, portions of a plurality of signal bonding pads, portions of a plurality of power bonding pads, portions of a plurality of row address decoders, portions of a plurality of column address decoders, and portions of a plurality of sense amplifiers;
• and
• one or more semiconductor interconnect layer interconnecting other portions of the single-bit memory cells, other portions of the plurality of row address decoders, other portions of the plurality of column address decoders and other portions of the sense amplifiers.