Semiconductor memory device and method of manufacture the same
AssigneeKabushiki Kaisha Toshiba
InventorKatsuhiko Hieda
Life of this patent
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Abstract
A semiconductor memory device includes a transistor having a gate electrode formed above a semiconductor substrate and source and drain regions formed in the semiconductor substrate, a bit line contact formed in an interlayer insulating film formed to cover the transistor and connected to one of the source and drain regions, a storage node electrode contact formed in the interlayer insulating film and connected to the other of the source and drain regions, a bit line contact plug formed on the bit line contact, a storage node electrode contact plug formed on the storage node electrode contact, a bit line formed to connect to the bit line contact plug, and a capacitor storage node electrode formed to connect to the storage node electrode contact plug.
Claims39
A semiconductor memory device comprising:
- a transistor having a gate electrode formed above a semiconductor substrate and source and drain regions formed in the semiconductor substrate;
- a first interlayer insulating film covering the transistor and having contact holes leading to the source region and the drain region, respectively;
- a bit line contact formed in one of the contact holes;
- a storage node electrode contact formed in the other of the contact holes;
- a bit line contact plug formed on the bit line contact;
- a storage node electrode contact plug comprising a first barrier metal layer formed on the storage node electrode contact and a first metal lay formed on the first barrier metal layer;
- a second interlayer insulating film formed on the first interlayer insulating film, the storage node electrode contact plug and a bit line contact plug being provided in the second interlayer insulating film;
- a first sidewall insulating film surrounding the first metal layer, and a material of the first sidewall insulating film being different from a material of the second interlayer insulating film;
- a bit line connected to the bit line contact plug;
- and
- a storage node electrode of a capacitor, connected to the storage node electrode contact plug,
- wherein the first barrier metal layer is only formed under the bottom face of the first metal layer.
A semiconductor memory device comprising:
- a transistor having a gate electrode formed above a semiconductor substrate and source and drain regions formed in the semiconductor substrate;
- a first interlayer insulating film covering the transistor and having contact holes leading to the source region and the drain region, respectively;
- a bit line contact formed in one of the contact holes;
- a storage node electrode contact formed in the other of the contact holes;
- a bit line contact plug formed on the bit line contact;
- a storage node electrode contact plug formed on the storage node electrode contact;
- a second interlayer insulating film formed on the first interlayer insulating film, the storage node electrode contact plug and the bit line contact plug being provided in the second interlayer insulating film;
- a first sidewall insulating film surrounding a first metal layer, and a material of the first sidewall insulating film being different from a material of the second interlayer insulating film;
- a bit line connected to the bit line contact plug;
- and
- a storage node electrode of a capacitor, connected to the storage node electrode contact plug.
A semiconductor memory device comprising:
- a translator having a gate electrode formed above a semiconductor substrate and source and drain regions formed in the semiconductor substrate;
- a first interlayer insulating film covering the transistor and having contact holes leading to the source region and the drain region, respectively;
- a bit line contact formed in one of the contact holes;
- a storage node electrode contact formed in the other of the contact holes;
- a bit line contact plug formed on the bit line contact;
- a storage node electrode contact plug having a first metal layer formed on the storage node electrode contact and a second metal layer formed on the first metal layer;
- a second interlayer insulating film formed on the first interlayer insulating film, the storage node electrode contact plug and the bit line contact plug being provided in the second interlayer insulating film;
- a first sidewall insulating film surrounding the first metal layer, and a material of the first sidewall insulating film being different from a material of the second interlayer insulating film;
- a bit line connected to the bit line contact plug;
- and
- a storage node electrode of a capacitor, connected to the storage node electrode contact plug.
Dependencies are inferred from the claim text.