Method of manufacturing a semiconductor device
AssigneeNEC Corporation
InventorHidemitsu Aoki
Life of this patent
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Abstract
In a method of manufacturing a semiconductor device having a multi-layer interconnection, after a via hole has been formed, the inside of the via hole is cleaned using a cleaning solution containing a complexing agent capable of forming a complex with contaminants of copper type metals.
Claims10
A method of manufacturing a semiconductor device comprising the steps of:
- (A) a step of forming, on a semiconductor substrate, a metal wiring made of a metal material containing copper or a copper alloy,
- (B) a step of forming an inter-layer insulating film on the metal wiring,
- (C) a step of forming, in the inter-layer insulating film, a via hole reaching the metal wiring by dry etching,
- (D) a step of removing contaminants which consist of the metal material and/or the compound(s) thereof and which have adhered to the inner wall of the via hole as a result of the dry etching, by using a cleaning solution consisting essentially of water and a complexing agent capable of forming a complex with the contaminants,
- (E) a step of forming a barrier metal film on the inner wall of the via hole and then forming an electrically conductive film on the whole surface of the resulting substrate so as to fill the via hole, and
- (F) a step of removing the unnecessary portions of the electrically conductive film and the barrier metal film, formed outside the via hole, by etching or chemical mechanical polishing to obtain a flat surface.
A method of manufacturing a semiconductor device having a copper wiring, which comprises, after formation of a via hole, cleaning the inside of the via hole using a cleaning solution consisting essentially of water and a complexing agent capable of forming a complex with contaminants of copper type metals.
Dependencies are inferred from the claim text.