Method of etching trenches for metallization of integrated circuit devices with a narrower width than the design mask profile

A method of metallization in the fabrication of an integrated circuit device comprising:

• providing a dielectric layer over a region to be contacted on a substrate wherein said dielectric layer has a dielectric constant of less than 3;
• depositing an undoped silicate glass (USG) layer overlying said dielectric layer;
• forming a mask over said USG layer wherein said mask has a first opening of a first width;
• etching a second opening in said USG layer where it is exposed by said mask wherein said second opening has a second width smaller than said first width and wherein said second opening has inwardly sloping sidewalls;
• etching a trench through said dielectric layer to said region to be contacted through said second opening whereby said trench has a width equal to said second width;
• and
• filling said trench with a metal layer and planarizing said metal layer to complete said metallization in said fabrication of said integrated circuit device.

A method of metallization in the fabrication of an integrated circuit device comprising:

• providing a dielectric layer over a region to be contacted on a substrate wherein said dielectric layer has a dielectric constant of less than 3;
• depositing an undoped silicate glass (USG) layer overlying said dielectric layer;
• forming a mask over said USG layer wherein said mask has a first opening of a first width;
• etching a second opening in said USG layer where it is exposed by said mask wherein said second opening has a second width smaller than said first width, wherein said second opening has inwardly sloping sidewalls and wherein said etching is performed using CF4, O2, and Ar gases with a wafer chuck temperature between 10 and 10° C. or below;
• etching a trench through said dielectric layer to said region to be contacted through said second opening whereby said trench has a width equal to said second width;
• and
• filling said trench with a metal layer and planarizing said metal layer to complete said metallization in said fabrication of said integrated circuit device.