Method to fabricate RF inductors with minimum area

A method for fabricating an RF inductor with copper damascene conducting coils, high Q and minimum area comprising:

• providing a substrate;
• forming on said substrate a first intermetal dielectric (IMD) layer;
• forming in said first IMD layer a plurality of parallel, equidistant linear trenches using a first patterned photolithography mask;
• forming in said trenches conducting segments having a copper damascene structure;
• forming over said first IMD layer a first barrier/etch stop layer;
• forming a second IMD layer over said first barrier/etch stop layer;
• patterning and etching said second IMD layer using a second patterned photolithography mask so as to form a plurality of parallel equidistant trenches extending vertically to the surface of said first low-K IMD, said trenches also being parallel to and dimensionally equivalent to the now copper damascene filled linear trenches formed within the IMD layer and wherein each trench in said second IMD layer is positioned above and between a pair of said copper damascene metal segments;
• forming a plurality of parallel copper damascene segments within said trenches formed in said second IMD layer;
• forming over said second IMD layer a second barrier/etch stop layer;
• forming over said second barrier/etch stop layer over said second planarized IMD layer a third IMD layer;
• planarizing said third IMD layer;
• forming and patterning a third photolithography mask on said third IMD layer;
• etching said third IMD layer through said third photolithography mask so as to form two sets of cylindrical vias, wherein one set is positioned over opposite ends of the copper damascene segments formed within the second IMD layer and extends completely through said third IMD layer and through said second barrier/etch stop layer over said second IMD layer and the second set is positioned over opposite ends of the copper damascene segments formed within the first IMD layer and extends completely through said third IMD layer, said second barrier/etch stop layer, said second IMD layer and said first barrier/etch stop layer;
• depositing conducting plugs within said vias so as to electrically contact said copper damascene segments within said first and second IMD layers;
• forming a fourth IMD layer over said third IMD layer;
• forming and patterning a fourth photolithography mask over said fourth IMD layer;
• forming in said fourth IMD layer, by etching through said patterned fourth photolithography mask, a plurality of approximately equidistant parallel trenches obliquely disposed relative to said copper damascene segments formed in said first and second IMD layers;
• forming copper damascene segments within said trenches wherein one end of each of said copper damascene segments makes electrical contact with a conductor filled via of one set of vias and the other end of said linear metal segment makes electrical contact with a conductor filled via belonging to the other set of vias formed in said third IMD and wherein said formation of linear copper damascene segments thereby produces a continuous electrically conductive helical path.