Method and circuit for controlling a first-in-first-out (FIFO) buffer using a bank of FIFO address registers capturing and saving beginning and ending write-pointer addresses

A method of controlling a first-in-first-out (FIFO) buffer circuit to manage the bi-directional transfer of data blocks between first and second asynchronous data handling systems, the FIFO buffer circuit including a FIFO buffer, a read-pointer register, a write-pointer register, and a buffer status register, the FIFO buffer circuit being coupled with the first and the second asynchronous systems, the FIFO buffer being further coupled with a bank of FIFO buffer address registers, the bank of FIFO buffer address registers including a first pair and a second pair of registers, the first pair of registers having a first start-write register and a first end-write register, the second pair of registers having a second start-write register and a second end-write register, the method comprising the steps of:

• A. enabling the first asynchronous system to write a first data block to the FIFO buffer;
• B. enabling a first read/write process control circuit for permitting a data segment of the first data block to be written to the FIFO buffer;
• C. determining if there is space available in the FIFO buffer for the data of the first data block to be written;
• D. saving a start-write address associated with the beginning of the first data block written to the FIFO buffer;
• E. writing the first data block to the FIFO buffer;
• F. incrementing the write-pointer address register as each data segment of the first data block is written to the FIFO buffer;
• G. detecting and saving an end-write address associated with the ending of the first data block written to the FIFO buffer, wherein the start-write address and the end-write address define the beginning and ending addresses of the first data block written to the FIFO buffer for enabling the FIFO buffer to accommodate more data blocks than the first data block simultaneously without data overlap;
• and
• H. determining if the first asynchronous system is being commanded to write another data block to the FIFO buffer, and if so, then repeating steps A through F, and if not, then ending.

A FIFO buffer circuit including a FIFO buffer for temporary storage of bounded data blocks of predetermined length being transferred asynchronously from a data source to a data destination, each data block having a data length in excess of a data storage capacity of the FIFO buffer, the FIFO buffer comprising addressable rows, each row for storing a segment of a said data block, the FIFO buffer circuit including:

• a write address register for pointing to each row of the FIFO buffer to be written by the data source in accordance with a write address,
• a read address register for pointing to each row of the FIFO buffer to be read by the data destination in accordance with a read address,
• a plurality of pairs of write-address capture registers communicating with the write address register and the read address register and comprising at least:
• a first capture register pair including a first write-start capture register for capturing an address corresponding to a starting row address of a first said data block, and a first write-end capture register for capturing an address corresponding to an ending row address of the first said data block, and
• a second capture register pair including a second write-start capture register for capturing an address corresponding to a starting row address of a second said data block, and a second write-end capture register for capturing an address corresponding to an ending row address of the second said data block;
• and
• FIFO buffer control means for controlling the plurality of pairs of write address capture registers and the write address register and the read address register for enabling segments of the first and second data blocks to be written to and read from rows of the FIFO buffer without overlap and without interruption at data block boundaries.